From: Sasha Levin Date: Sun, 25 Sep 2022 14:30:24 +0000 (-0400) Subject: Fixes for 5.19 X-Git-Tag: v4.9.330~47 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cd35dd19cd184cad73faaec5b2691ce6a80756bc;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.19 Signed-off-by: Sasha Levin --- diff --git a/queue-5.19/drivers-hv-never-allocate-anything-besides-framebuff.patch b/queue-5.19/drivers-hv-never-allocate-anything-besides-framebuff.patch new file mode 100644 index 00000000000..c56abb71064 --- /dev/null +++ b/queue-5.19/drivers-hv-never-allocate-anything-besides-framebuff.patch @@ -0,0 +1,101 @@ +From fdf04720781e95992530cde49c182d351f319b61 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 27 Aug 2022 15:03:45 +0200 +Subject: Drivers: hv: Never allocate anything besides framebuffer from + framebuffer memory region + +From: Vitaly Kuznetsov + +[ Upstream commit f0880e2cb7e1f8039a048fdd01ce45ab77247221 ] + +Passed through PCI device sometimes misbehave on Gen1 VMs when Hyper-V +DRM driver is also loaded. Looking at IOMEM assignment, we can see e.g. + +$ cat /proc/iomem +... +f8000000-fffbffff : PCI Bus 0000:00 + f8000000-fbffffff : 0000:00:08.0 + f8000000-f8001fff : bb8c4f33-2ba2-4808-9f7f-02f3b4da22fe +... +fe0000000-fffffffff : PCI Bus 0000:00 + fe0000000-fe07fffff : bb8c4f33-2ba2-4808-9f7f-02f3b4da22fe + fe0000000-fe07fffff : 2ba2:00:02.0 + fe0000000-fe07fffff : mlx4_core + +the interesting part is the 'f8000000' region as it is actually the +VM's framebuffer: + +$ lspci -v +... +0000:00:08.0 VGA compatible controller: Microsoft Corporation Hyper-V virtual VGA (prog-if 00 [VGA controller]) + Flags: bus master, fast devsel, latency 0, IRQ 11 + Memory at f8000000 (32-bit, non-prefetchable) [size=64M] +... + + hv_vmbus: registering driver hyperv_drm + hyperv_drm 5620e0c7-8062-4dce-aeb7-520c7ef76171: [drm] Synthvid Version major 3, minor 5 + hyperv_drm 0000:00:08.0: vgaarb: deactivate vga console + hyperv_drm 0000:00:08.0: BAR 0: can't reserve [mem 0xf8000000-0xfbffffff] + hyperv_drm 5620e0c7-8062-4dce-aeb7-520c7ef76171: [drm] Cannot request framebuffer, boot fb still active? + +Note: "Cannot request framebuffer" is not a fatal error in +hyperv_setup_gen1() as the code assumes there's some other framebuffer +device there but we actually have some other PCI device (mlx4 in this +case) config space there! + +The problem appears to be that vmbus_allocate_mmio() can use dedicated +framebuffer region to serve any MMIO request from any device. The +semantics one might assume of a parameter named "fb_overlap_ok" +aren't implemented because !fb_overlap_ok essentially has no effect. +The existing semantics are really "prefer_fb_overlap". This patch +implements the expected and needed semantics, which is to not allocate +from the frame buffer space when !fb_overlap_ok. + +Note, Gen2 VMs are usually unaffected by the issue because +framebuffer region is already taken by EFI fb (in case kernel supports +it) but Gen1 VMs may have this region unclaimed by the time Hyper-V PCI +pass-through driver tries allocating MMIO space if Hyper-V DRM/FB drivers +load after it. Devices can be brought up in any sequence so let's +resolve the issue by always ignoring 'fb_mmio' region for non-FB +requests, even if the region is unclaimed. + +Reviewed-by: Michael Kelley +Signed-off-by: Vitaly Kuznetsov +Link: https://lore.kernel.org/r/20220827130345.1320254-4-vkuznets@redhat.com +Signed-off-by: Wei Liu +Signed-off-by: Sasha Levin +--- + drivers/hv/vmbus_drv.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c +index 547ae334e5cd..027029efb008 100644 +--- a/drivers/hv/vmbus_drv.c ++++ b/drivers/hv/vmbus_drv.c +@@ -2309,7 +2309,7 @@ int vmbus_allocate_mmio(struct resource **new, struct hv_device *device_obj, + bool fb_overlap_ok) + { + struct resource *iter, *shadow; +- resource_size_t range_min, range_max, start; ++ resource_size_t range_min, range_max, start, end; + const char *dev_n = dev_name(&device_obj->device); + int retval; + +@@ -2344,6 +2344,14 @@ int vmbus_allocate_mmio(struct resource **new, struct hv_device *device_obj, + range_max = iter->end; + start = (range_min + align - 1) & ~(align - 1); + for (; start + size - 1 <= range_max; start += align) { ++ end = start + size - 1; ++ ++ /* Skip the whole fb_mmio region if not fb_overlap_ok */ ++ if (!fb_overlap_ok && fb_mmio && ++ (((start >= fb_mmio->start) && (start <= fb_mmio->end)) || ++ ((end >= fb_mmio->start) && (end <= fb_mmio->end)))) ++ continue; ++ + shadow = __request_region(iter, start, size, NULL, + IORESOURCE_BUSY); + if (!shadow) +-- +2.35.1 + diff --git a/queue-5.19/drm-amd-display-limit-user-regamma-to-a-valid-value.patch b/queue-5.19/drm-amd-display-limit-user-regamma-to-a-valid-value.patch new file mode 100644 index 00000000000..df6357de238 --- /dev/null +++ b/queue-5.19/drm-amd-display-limit-user-regamma-to-a-valid-value.patch @@ -0,0 +1,55 @@ +From efa6640a9c85c291a7b9756d6c659637d3e4ebb3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 22 Aug 2022 18:30:31 +0800 +Subject: drm/amd/display: Limit user regamma to a valid value + +From: Yao Wang1 + +[ Upstream commit 3601d620f22e37740cf73f8278eabf9f2aa19eb7 ] + +[Why] +For HDR mode, we get total 512 tf_point and after switching to SDR mode +we actually get 400 tf_point and the rest of points(401~512) still use +dirty value from HDR mode. We should limit the rest of the points to max +value. + +[How] +Limit the value when coordinates_x.x > 1, just like what we do in +translate_from_linear_space for other re-gamma build paths. + +Tested-by: Daniel Wheeler +Reviewed-by: Krunoslav Kovac +Reviewed-by: Aric Cyr +Acked-by: Pavle Kotarac +Signed-off-by: Yao Wang1 +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +index 64a38f08f497..5a51be753e87 100644 +--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c ++++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c +@@ -1603,6 +1603,7 @@ static void interpolate_user_regamma(uint32_t hw_points_num, + struct fixed31_32 lut2; + struct fixed31_32 delta_lut; + struct fixed31_32 delta_index; ++ const struct fixed31_32 one = dc_fixpt_from_int(1); + + i = 0; + /* fixed_pt library has problems handling too small values */ +@@ -1631,6 +1632,9 @@ static void interpolate_user_regamma(uint32_t hw_points_num, + } else + hw_x = coordinates_x[i].x; + ++ if (dc_fixpt_le(one, hw_x)) ++ hw_x = one; ++ + norm_x = dc_fixpt_mul(norm_factor, hw_x); + index = dc_fixpt_floor(norm_x); + if (index < 0 || index > 255) +-- +2.35.1 + diff --git a/queue-5.19/drm-amd-display-mark-dml30-s-useminimumdcfclk-as-noi.patch b/queue-5.19/drm-amd-display-mark-dml30-s-useminimumdcfclk-as-noi.patch new file mode 100644 index 00000000000..eb45f867cf8 --- /dev/null +++ b/queue-5.19/drm-amd-display-mark-dml30-s-useminimumdcfclk-as-noi.patch @@ -0,0 +1,62 @@ +From f9c245b77506b8b7d90654b5bb1ca3e991fd7b5a Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 13:34:09 -0700 +Subject: drm/amd/display: Mark dml30's UseMinimumDCFCLK() as noinline for + stack usage +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nathan Chancellor + +[ Upstream commit 41012d715d5d7b9751ae84b8fb255e404ac9c5d0 ] + +This function consumes a lot of stack space and it blows up the size of +dml30_ModeSupportAndSystemConfigurationFull() with clang: + + drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.c:3542:6: error: stack frame size (2200) exceeds limit (2048) in 'dml30_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] + void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) + ^ + 1 error generated. + +Commit a0f7e7f759cf ("drm/amd/display: fix i386 frame size warning") +aimed to address this for i386 but it did not help x86_64. + +To reduce the amount of stack space that +dml30_ModeSupportAndSystemConfigurationFull() uses, mark +UseMinimumDCFCLK() as noinline, using the _for_stack variant for +documentation. While this will increase the total amount of stack usage +between the two functions (1632 and 1304 bytes respectively), it will +make sure both stay below the limit of 2048 bytes for these files. The +aforementioned change does help reduce UseMinimumDCFCLK()'s stack usage +so it should not be reverted in favor of this change. + +Link: https://github.com/ClangBuiltLinux/linux/issues/1681 +Reported-by: "Sudip Mukherjee (Codethink)" +Tested-by: Maíra Canal +Reviewed-by: Rodrigo Siqueira +Signed-off-by: Nathan Chancellor +Signed-off-by: Rodrigo Siqueira +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +index f47d82da115c..42a567e71439 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +@@ -6651,8 +6651,7 @@ static double CalculateUrgentLatency( + return ret; + } + +- +-static void UseMinimumDCFCLK( ++static noinline_for_stack void UseMinimumDCFCLK( + struct display_mode_lib *mode_lib, + int MaxInterDCNTileRepeaters, + int MaxPrefetchMode, +-- +2.35.1 + diff --git a/queue-5.19/drm-amd-display-reduce-number-of-arguments-of-dml31-.patch b/queue-5.19/drm-amd-display-reduce-number-of-arguments-of-dml31-.patch new file mode 100644 index 00000000000..e62b6db161a --- /dev/null +++ b/queue-5.19/drm-amd-display-reduce-number-of-arguments-of-dml31-.patch @@ -0,0 +1,512 @@ +From d7905462a02a772c486977c5466a2d8d476b6b97 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 13:34:07 -0700 +Subject: drm/amd/display: Reduce number of arguments of dml31's + CalculateWatermarksAndDRAMSpeedChangeSupport() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nathan Chancellor + +[ Upstream commit 37934d4118e22bceb80141804391975078f31734 ] + +Most of the arguments are identical between the two call sites and they +can be accessed through the 'struct vba_vars_st' pointer. This reduces +the total amount of stack space that +dml31_ModeSupportAndSystemConfigurationFull() uses by 240 bytes with +LLVM 16 (2216 -> 1976), helping clear up the following clang warning: + + drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:3908:6: error: stack frame size (2216) exceeds limit (2048) in 'dml31_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] + void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) + ^ + 1 error generated. + +Link: https://github.com/ClangBuiltLinux/linux/issues/1681 +Reported-by: "Sudip Mukherjee (Codethink)" +Tested-by: Maíra Canal +Reviewed-by: Rodrigo Siqueira +Signed-off-by: Nathan Chancellor +Signed-off-by: Rodrigo Siqueira +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + .../dc/dml/dcn31/display_mode_vba_31.c | 248 ++++-------------- + 1 file changed, 52 insertions(+), 196 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +index e4b9fd31223c..586825d85d66 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +@@ -321,64 +321,28 @@ static void CalculateVupdateAndDynamicMetadataParameters( + static void CalculateWatermarksAndDRAMSpeedChangeSupport( + struct display_mode_lib *mode_lib, + unsigned int PrefetchMode, +- unsigned int NumberOfActivePlanes, +- unsigned int MaxLineBufferLines, +- unsigned int LineBufferSize, +- unsigned int WritebackInterfaceBufferSize, + double DCFCLK, + double ReturnBW, +- bool SynchronizedVBlank, +- unsigned int dpte_group_bytes[], +- unsigned int MetaChunkSize, + double UrgentLatency, + double ExtraLatency, +- double WritebackLatency, +- double WritebackChunkSize, + double SOCCLK, +- double DRAMClockChangeLatency, +- double SRExitTime, +- double SREnterPlusExitTime, +- double SRExitZ8Time, +- double SREnterPlusExitZ8Time, + double DCFCLKDeepSleep, + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], +- unsigned int LBBitPerPixel[], + double SwathWidthY[], + double SwathWidthC[], +- double HRatio[], +- double HRatioChroma[], +- unsigned int vtaps[], +- unsigned int VTAPsChroma[], +- double VRatio[], +- double VRatioChroma[], +- unsigned int HTotal[], +- double PixelClock[], +- unsigned int BlendingAndTiming[], + unsigned int DPPPerPlane[], + double BytePerPixelDETY[], + double BytePerPixelDETC[], +- double DSTXAfterScaler[], +- double DSTYAfterScaler[], +- bool WritebackEnable[], +- enum source_format_class WritebackPixelFormat[], +- double WritebackDestinationWidth[], +- double WritebackDestinationHeight[], +- double WritebackSourceHeight[], + bool UnboundedRequestEnabled, + int unsigned CompressedBufferSizeInkByte, + enum clock_change_support *DRAMClockChangeSupport, +- double *UrgentWatermark, +- double *WritebackUrgentWatermark, +- double *DRAMClockChangeWatermark, +- double *WritebackDRAMClockChangeWatermark, + double *StutterExitWatermark, + double *StutterEnterPlusExitWatermark, + double *Z8StutterExitWatermark, +- double *Z8StutterEnterPlusExitWatermark, +- double *MinActiveDRAMClockChangeLatencySupported); ++ double *Z8StutterEnterPlusExitWatermark); + + static void CalculateDCFCLKDeepSleep( + struct display_mode_lib *mode_lib, +@@ -3027,64 +2991,28 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman + CalculateWatermarksAndDRAMSpeedChangeSupport( + mode_lib, + PrefetchMode, +- v->NumberOfActivePlanes, +- v->MaxLineBufferLines, +- v->LineBufferSize, +- v->WritebackInterfaceBufferSize, + v->DCFCLK, + v->ReturnBW, +- v->SynchronizedVBlank, +- v->dpte_group_bytes, +- v->MetaChunkSize, + v->UrgentLatency, + v->UrgentExtraLatency, +- v->WritebackLatency, +- v->WritebackChunkSize, + v->SOCCLK, +- v->DRAMClockChangeLatency, +- v->SRExitTime, +- v->SREnterPlusExitTime, +- v->SRExitZ8Time, +- v->SREnterPlusExitZ8Time, + v->DCFCLKDeepSleep, + v->DETBufferSizeY, + v->DETBufferSizeC, + v->SwathHeightY, + v->SwathHeightC, +- v->LBBitPerPixel, + v->SwathWidthY, + v->SwathWidthC, +- v->HRatio, +- v->HRatioChroma, +- v->vtaps, +- v->VTAPsChroma, +- v->VRatio, +- v->VRatioChroma, +- v->HTotal, +- v->PixelClock, +- v->BlendingAndTiming, + v->DPPPerPlane, + v->BytePerPixelDETY, + v->BytePerPixelDETC, +- v->DSTXAfterScaler, +- v->DSTYAfterScaler, +- v->WritebackEnable, +- v->WritebackPixelFormat, +- v->WritebackDestinationWidth, +- v->WritebackDestinationHeight, +- v->WritebackSourceHeight, + v->UnboundedRequestEnabled, + v->CompressedBufferSizeInkByte, + &DRAMClockChangeSupport, +- &v->UrgentWatermark, +- &v->WritebackUrgentWatermark, +- &v->DRAMClockChangeWatermark, +- &v->WritebackDRAMClockChangeWatermark, + &v->StutterExitWatermark, + &v->StutterEnterPlusExitWatermark, + &v->Z8StutterExitWatermark, +- &v->Z8StutterEnterPlusExitWatermark, +- &v->MinActiveDRAMClockChangeLatencySupported); ++ &v->Z8StutterEnterPlusExitWatermark); + + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->WritebackEnable[k] == true) { +@@ -5481,64 +5409,28 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l + CalculateWatermarksAndDRAMSpeedChangeSupport( + mode_lib, + v->PrefetchModePerState[i][j], +- v->NumberOfActivePlanes, +- v->MaxLineBufferLines, +- v->LineBufferSize, +- v->WritebackInterfaceBufferSize, + v->DCFCLKState[i][j], + v->ReturnBWPerState[i][j], +- v->SynchronizedVBlank, +- v->dpte_group_bytes, +- v->MetaChunkSize, + v->UrgLatency[i], + v->ExtraLatency, +- v->WritebackLatency, +- v->WritebackChunkSize, + v->SOCCLKPerState[i], +- v->DRAMClockChangeLatency, +- v->SRExitTime, +- v->SREnterPlusExitTime, +- v->SRExitZ8Time, +- v->SREnterPlusExitZ8Time, + v->ProjectedDCFCLKDeepSleep[i][j], + v->DETBufferSizeYThisState, + v->DETBufferSizeCThisState, + v->SwathHeightYThisState, + v->SwathHeightCThisState, +- v->LBBitPerPixel, + v->SwathWidthYThisState, + v->SwathWidthCThisState, +- v->HRatio, +- v->HRatioChroma, +- v->vtaps, +- v->VTAPsChroma, +- v->VRatio, +- v->VRatioChroma, +- v->HTotal, +- v->PixelClock, +- v->BlendingAndTiming, + v->NoOfDPPThisState, + v->BytePerPixelInDETY, + v->BytePerPixelInDETC, +- v->DSTXAfterScaler, +- v->DSTYAfterScaler, +- v->WritebackEnable, +- v->WritebackPixelFormat, +- v->WritebackDestinationWidth, +- v->WritebackDestinationHeight, +- v->WritebackSourceHeight, + UnboundedRequestEnabledThisState, + CompressedBufferSizeInkByteThisState, + &v->DRAMClockChangeSupport[i][j], +- &v->UrgentWatermark, +- &v->WritebackUrgentWatermark, +- &v->DRAMClockChangeWatermark, +- &v->WritebackDRAMClockChangeWatermark, +- &dummy, + &dummy, + &dummy, + &dummy, +- &v->MinActiveDRAMClockChangeLatencySupported); ++ &dummy); + } + } + +@@ -5663,64 +5555,28 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l + static void CalculateWatermarksAndDRAMSpeedChangeSupport( + struct display_mode_lib *mode_lib, + unsigned int PrefetchMode, +- unsigned int NumberOfActivePlanes, +- unsigned int MaxLineBufferLines, +- unsigned int LineBufferSize, +- unsigned int WritebackInterfaceBufferSize, + double DCFCLK, + double ReturnBW, +- bool SynchronizedVBlank, +- unsigned int dpte_group_bytes[], +- unsigned int MetaChunkSize, + double UrgentLatency, + double ExtraLatency, +- double WritebackLatency, +- double WritebackChunkSize, + double SOCCLK, +- double DRAMClockChangeLatency, +- double SRExitTime, +- double SREnterPlusExitTime, +- double SRExitZ8Time, +- double SREnterPlusExitZ8Time, + double DCFCLKDeepSleep, + unsigned int DETBufferSizeY[], + unsigned int DETBufferSizeC[], + unsigned int SwathHeightY[], + unsigned int SwathHeightC[], +- unsigned int LBBitPerPixel[], + double SwathWidthY[], + double SwathWidthC[], +- double HRatio[], +- double HRatioChroma[], +- unsigned int vtaps[], +- unsigned int VTAPsChroma[], +- double VRatio[], +- double VRatioChroma[], +- unsigned int HTotal[], +- double PixelClock[], +- unsigned int BlendingAndTiming[], + unsigned int DPPPerPlane[], + double BytePerPixelDETY[], + double BytePerPixelDETC[], +- double DSTXAfterScaler[], +- double DSTYAfterScaler[], +- bool WritebackEnable[], +- enum source_format_class WritebackPixelFormat[], +- double WritebackDestinationWidth[], +- double WritebackDestinationHeight[], +- double WritebackSourceHeight[], + bool UnboundedRequestEnabled, + int unsigned CompressedBufferSizeInkByte, + enum clock_change_support *DRAMClockChangeSupport, +- double *UrgentWatermark, +- double *WritebackUrgentWatermark, +- double *DRAMClockChangeWatermark, +- double *WritebackDRAMClockChangeWatermark, + double *StutterExitWatermark, + double *StutterEnterPlusExitWatermark, + double *Z8StutterExitWatermark, +- double *Z8StutterEnterPlusExitWatermark, +- double *MinActiveDRAMClockChangeLatencySupported) ++ double *Z8StutterEnterPlusExitWatermark) + { + struct vba_vars_st *v = &mode_lib->vba; + double EffectiveLBLatencyHidingY; +@@ -5740,103 +5596,103 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( + double TotalPixelBW = 0.0; + int k, j; + +- *UrgentWatermark = UrgentLatency + ExtraLatency; ++ v->UrgentWatermark = UrgentLatency + ExtraLatency; + + #ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: UrgentLatency = %f\n", __func__, UrgentLatency); + dml_print("DML::%s: ExtraLatency = %f\n", __func__, ExtraLatency); +- dml_print("DML::%s: UrgentWatermark = %f\n", __func__, *UrgentWatermark); ++ dml_print("DML::%s: UrgentWatermark = %f\n", __func__, v->UrgentWatermark); + #endif + +- *DRAMClockChangeWatermark = DRAMClockChangeLatency + *UrgentWatermark; ++ v->DRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->UrgentWatermark; + + #ifdef __DML_VBA_DEBUG__ +- dml_print("DML::%s: DRAMClockChangeLatency = %f\n", __func__, DRAMClockChangeLatency); +- dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, *DRAMClockChangeWatermark); ++ dml_print("DML::%s: v->DRAMClockChangeLatency = %f\n", __func__, v->DRAMClockChangeLatency); ++ dml_print("DML::%s: DRAMClockChangeWatermark = %f\n", __func__, v->DRAMClockChangeWatermark); + #endif + + v->TotalActiveWriteback = 0; +- for (k = 0; k < NumberOfActivePlanes; ++k) { +- if (WritebackEnable[k] == true) { ++ for (k = 0; k < v->NumberOfActivePlanes; ++k) { ++ if (v->WritebackEnable[k] == true) { + v->TotalActiveWriteback = v->TotalActiveWriteback + 1; + } + } + + if (v->TotalActiveWriteback <= 1) { +- *WritebackUrgentWatermark = WritebackLatency; ++ v->WritebackUrgentWatermark = v->WritebackLatency; + } else { +- *WritebackUrgentWatermark = WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; ++ v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; + } + + if (v->TotalActiveWriteback <= 1) { +- *WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency; ++ v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency; + } else { +- *WritebackDRAMClockChangeWatermark = DRAMClockChangeLatency + WritebackLatency + WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; ++ v->WritebackDRAMClockChangeWatermark = v->DRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK; + } + +- for (k = 0; k < NumberOfActivePlanes; ++k) { ++ for (k = 0; k < v->NumberOfActivePlanes; ++k) { + TotalPixelBW = TotalPixelBW +- + DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * VRatioChroma[k]) +- / (HTotal[k] / PixelClock[k]); ++ + DPPPerPlane[k] * (SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] + SwathWidthC[k] * BytePerPixelDETC[k] * v->VRatioChroma[k]) ++ / (v->HTotal[k] / v->PixelClock[k]); + } + +- for (k = 0; k < NumberOfActivePlanes; ++k) { ++ for (k = 0; k < v->NumberOfActivePlanes; ++k) { + double EffectiveDETBufferSizeY = DETBufferSizeY[k]; + + v->LBLatencyHidingSourceLinesY = dml_min( +- (double) MaxLineBufferLines, +- dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(HRatio[k], 1.0)), 1)) - (vtaps[k] - 1); ++ (double) v->MaxLineBufferLines, ++ dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthY[k] / dml_max(v->HRatio[k], 1.0)), 1)) - (v->vtaps[k] - 1); + + v->LBLatencyHidingSourceLinesC = dml_min( +- (double) MaxLineBufferLines, +- dml_floor(LineBufferSize / LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(HRatioChroma[k], 1.0)), 1)) - (VTAPsChroma[k] - 1); ++ (double) v->MaxLineBufferLines, ++ dml_floor(v->LineBufferSize / v->LBBitPerPixel[k] / (SwathWidthC[k] / dml_max(v->HRatioChroma[k], 1.0)), 1)) - (v->VTAPsChroma[k] - 1); + +- EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / VRatio[k] * (HTotal[k] / PixelClock[k]); ++ EffectiveLBLatencyHidingY = v->LBLatencyHidingSourceLinesY / v->VRatio[k] * (v->HTotal[k] / v->PixelClock[k]); + +- EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / VRatioChroma[k] * (HTotal[k] / PixelClock[k]); ++ EffectiveLBLatencyHidingC = v->LBLatencyHidingSourceLinesC / v->VRatioChroma[k] * (v->HTotal[k] / v->PixelClock[k]); + + if (UnboundedRequestEnabled) { + EffectiveDETBufferSizeY = EffectiveDETBufferSizeY +- + CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * VRatio[k] / (HTotal[k] / PixelClock[k]) / TotalPixelBW; ++ + CompressedBufferSizeInkByte * 1024 * SwathWidthY[k] * BytePerPixelDETY[k] * v->VRatio[k] / (v->HTotal[k] / v->PixelClock[k]) / TotalPixelBW; + } + + LinesInDETY[k] = (double) EffectiveDETBufferSizeY / BytePerPixelDETY[k] / SwathWidthY[k]; + LinesInDETYRoundedDownToSwath[k] = dml_floor(LinesInDETY[k], SwathHeightY[k]); +- FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (HTotal[k] / PixelClock[k]) / VRatio[k]; ++ FullDETBufferingTimeY = LinesInDETYRoundedDownToSwath[k] * (v->HTotal[k] / v->PixelClock[k]) / v->VRatio[k]; + if (BytePerPixelDETC[k] > 0) { + LinesInDETC = v->DETBufferSizeC[k] / BytePerPixelDETC[k] / SwathWidthC[k]; + LinesInDETCRoundedDownToSwath = dml_floor(LinesInDETC, SwathHeightC[k]); +- FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (HTotal[k] / PixelClock[k]) / VRatioChroma[k]; ++ FullDETBufferingTimeC = LinesInDETCRoundedDownToSwath * (v->HTotal[k] / v->PixelClock[k]) / v->VRatioChroma[k]; + } else { + LinesInDETC = 0; + FullDETBufferingTimeC = 999999; + } + + ActiveDRAMClockChangeLatencyMarginY = EffectiveLBLatencyHidingY + FullDETBufferingTimeY +- - ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark; ++ - ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark; + +- if (NumberOfActivePlanes > 1) { ++ if (v->NumberOfActivePlanes > 1) { + ActiveDRAMClockChangeLatencyMarginY = ActiveDRAMClockChangeLatencyMarginY +- - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightY[k] * HTotal[k] / PixelClock[k] / VRatio[k]; ++ - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightY[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatio[k]; + } + + if (BytePerPixelDETC[k] > 0) { + ActiveDRAMClockChangeLatencyMarginC = EffectiveLBLatencyHidingC + FullDETBufferingTimeC +- - ((double) DSTXAfterScaler[k] / HTotal[k] + DSTYAfterScaler[k]) * HTotal[k] / PixelClock[k] - *UrgentWatermark - *DRAMClockChangeWatermark; ++ - ((double) v->DSTXAfterScaler[k] / v->HTotal[k] + v->DSTYAfterScaler[k]) * v->HTotal[k] / v->PixelClock[k] - v->UrgentWatermark - v->DRAMClockChangeWatermark; + +- if (NumberOfActivePlanes > 1) { ++ if (v->NumberOfActivePlanes > 1) { + ActiveDRAMClockChangeLatencyMarginC = ActiveDRAMClockChangeLatencyMarginC +- - (1 - 1.0 / NumberOfActivePlanes) * SwathHeightC[k] * HTotal[k] / PixelClock[k] / VRatioChroma[k]; ++ - (1 - 1.0 / v->NumberOfActivePlanes) * SwathHeightC[k] * v->HTotal[k] / v->PixelClock[k] / v->VRatioChroma[k]; + } + v->ActiveDRAMClockChangeLatencyMargin[k] = dml_min(ActiveDRAMClockChangeLatencyMarginY, ActiveDRAMClockChangeLatencyMarginC); + } else { + v->ActiveDRAMClockChangeLatencyMargin[k] = ActiveDRAMClockChangeLatencyMarginY; + } + +- if (WritebackEnable[k] == true) { +- WritebackDRAMClockChangeLatencyHiding = WritebackInterfaceBufferSize * 1024 +- / (WritebackDestinationWidth[k] * WritebackDestinationHeight[k] / (WritebackSourceHeight[k] * HTotal[k] / PixelClock[k]) * 4); +- if (WritebackPixelFormat[k] == dm_444_64) { ++ if (v->WritebackEnable[k] == true) { ++ WritebackDRAMClockChangeLatencyHiding = v->WritebackInterfaceBufferSize * 1024 ++ / (v->WritebackDestinationWidth[k] * v->WritebackDestinationHeight[k] / (v->WritebackSourceHeight[k] * v->HTotal[k] / v->PixelClock[k]) * 4); ++ if (v->WritebackPixelFormat[k] == dm_444_64) { + WritebackDRAMClockChangeLatencyHiding = WritebackDRAMClockChangeLatencyHiding / 2; + } + WritebackDRAMClockChangeLatencyMargin = WritebackDRAMClockChangeLatencyHiding - v->WritebackDRAMClockChangeWatermark; +@@ -5846,14 +5702,14 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( + + v->MinActiveDRAMClockChangeMargin = 999999; + PlaneWithMinActiveDRAMClockChangeMargin = 0; +- for (k = 0; k < NumberOfActivePlanes; ++k) { ++ for (k = 0; k < v->NumberOfActivePlanes; ++k) { + if (v->ActiveDRAMClockChangeLatencyMargin[k] < v->MinActiveDRAMClockChangeMargin) { + v->MinActiveDRAMClockChangeMargin = v->ActiveDRAMClockChangeLatencyMargin[k]; +- if (BlendingAndTiming[k] == k) { ++ if (v->BlendingAndTiming[k] == k) { + PlaneWithMinActiveDRAMClockChangeMargin = k; + } else { +- for (j = 0; j < NumberOfActivePlanes; ++j) { +- if (BlendingAndTiming[k] == j) { ++ for (j = 0; j < v->NumberOfActivePlanes; ++j) { ++ if (v->BlendingAndTiming[k] == j) { + PlaneWithMinActiveDRAMClockChangeMargin = j; + } + } +@@ -5861,11 +5717,11 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( + } + } + +- *MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + DRAMClockChangeLatency; ++ v->MinActiveDRAMClockChangeLatencySupported = v->MinActiveDRAMClockChangeMargin + v->DRAMClockChangeLatency ; + + SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = 999999; +- for (k = 0; k < NumberOfActivePlanes; ++k) { +- if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (BlendingAndTiming[k] == k)) && !(BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) ++ for (k = 0; k < v->NumberOfActivePlanes; ++k) { ++ if (!((k == PlaneWithMinActiveDRAMClockChangeMargin) && (v->BlendingAndTiming[k] == k)) && !(v->BlendingAndTiming[k] == PlaneWithMinActiveDRAMClockChangeMargin) + && v->ActiveDRAMClockChangeLatencyMargin[k] < SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank) { + SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank = v->ActiveDRAMClockChangeLatencyMargin[k]; + } +@@ -5873,25 +5729,25 @@ static void CalculateWatermarksAndDRAMSpeedChangeSupport( + + v->TotalNumberOfActiveOTG = 0; + +- for (k = 0; k < NumberOfActivePlanes; ++k) { +- if (BlendingAndTiming[k] == k) { ++ for (k = 0; k < v->NumberOfActivePlanes; ++k) { ++ if (v->BlendingAndTiming[k] == k) { + v->TotalNumberOfActiveOTG = v->TotalNumberOfActiveOTG + 1; + } + } + + if (v->MinActiveDRAMClockChangeMargin > 0 && PrefetchMode == 0) { + *DRAMClockChangeSupport = dm_dram_clock_change_vactive; +- } else if ((SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1 ++ } else if ((v->SynchronizedVBlank == true || v->TotalNumberOfActiveOTG == 1 + || SecondMinActiveDRAMClockChangeMarginOneDisplayInVBLank > 0) && PrefetchMode == 0) { + *DRAMClockChangeSupport = dm_dram_clock_change_vblank; + } else { + *DRAMClockChangeSupport = dm_dram_clock_change_unsupported; + } + +- *StutterExitWatermark = SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep; +- *StutterEnterPlusExitWatermark = (SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep); +- *Z8StutterExitWatermark = SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; +- *Z8StutterEnterPlusExitWatermark = SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; ++ *StutterExitWatermark = v->SRExitTime + ExtraLatency + 10 / DCFCLKDeepSleep; ++ *StutterEnterPlusExitWatermark = (v->SREnterPlusExitTime + ExtraLatency + 10 / DCFCLKDeepSleep); ++ *Z8StutterExitWatermark = v->SRExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; ++ *Z8StutterEnterPlusExitWatermark = v->SREnterPlusExitZ8Time + ExtraLatency + 10 / DCFCLKDeepSleep; + + #ifdef __DML_VBA_DEBUG__ + dml_print("DML::%s: StutterExitWatermark = %f\n", __func__, *StutterExitWatermark); +-- +2.35.1 + diff --git a/queue-5.19/drm-amd-display-reduce-number-of-arguments-of-dml31-.patch-21191 b/queue-5.19/drm-amd-display-reduce-number-of-arguments-of-dml31-.patch-21191 new file mode 100644 index 00000000000..8343a6688c7 --- /dev/null +++ b/queue-5.19/drm-amd-display-reduce-number-of-arguments-of-dml31-.patch-21191 @@ -0,0 +1,309 @@ +From b3b5a01f11bba97f3f61962c1457e30f00f94f9c Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 13:34:08 -0700 +Subject: drm/amd/display: Reduce number of arguments of dml31's + CalculateFlipSchedule() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Nathan Chancellor + +[ Upstream commit 21485d3da659b66c37d99071623af83ee1c6733d ] + +Most of the arguments are identical between the two call sites and they +can be accessed through the 'struct vba_vars_st' pointer. This reduces +the total amount of stack space that +dml31_ModeSupportAndSystemConfigurationFull() uses by 112 bytes with +LLVM 16 (1976 -> 1864), helping clear up the following clang warning: + + drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.c:3908:6: error: stack frame size (2216) exceeds limit (2048) in 'dml31_ModeSupportAndSystemConfigurationFull' [-Werror,-Wframe-larger-than] + void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib) + ^ + 1 error generated. + +Link: https://github.com/ClangBuiltLinux/linux/issues/1681 +Reported-by: "Sudip Mukherjee (Codethink)" +Tested-by: Maíra Canal +Reviewed-by: Rodrigo Siqueira +Signed-off-by: Nathan Chancellor +Signed-off-by: Rodrigo Siqueira +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + .../dc/dml/dcn31/display_mode_vba_31.c | 172 +++++------------- + 1 file changed, 47 insertions(+), 125 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +index 586825d85d66..40a672236198 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c ++++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +@@ -261,33 +261,13 @@ static void CalculateRowBandwidth( + + static void CalculateFlipSchedule( + struct display_mode_lib *mode_lib, ++ unsigned int k, + double HostVMInefficiencyFactor, + double UrgentExtraLatency, + double UrgentLatency, +- unsigned int GPUVMMaxPageTableLevels, +- bool HostVMEnable, +- unsigned int HostVMMaxNonCachedPageTableLevels, +- bool GPUVMEnable, +- double HostVMMinPageSize, + double PDEAndMetaPTEBytesPerFrame, + double MetaRowBytes, +- double DPTEBytesPerRow, +- double BandwidthAvailableForImmediateFlip, +- unsigned int TotImmediateFlipBytes, +- enum source_format_class SourcePixelFormat, +- double LineTime, +- double VRatio, +- double VRatioChroma, +- double Tno_bw, +- bool DCCEnable, +- unsigned int dpte_row_height, +- unsigned int meta_row_height, +- unsigned int dpte_row_height_chroma, +- unsigned int meta_row_height_chroma, +- double *DestinationLinesToRequestVMInImmediateFlip, +- double *DestinationLinesToRequestRowInImmediateFlip, +- double *final_flip_bw, +- bool *ImmediateFlipSupportedForPipe); ++ double DPTEBytesPerRow); + static double CalculateWriteBackDelay( + enum source_format_class WritebackPixelFormat, + double WritebackHRatio, +@@ -2878,33 +2858,13 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman + for (k = 0; k < v->NumberOfActivePlanes; ++k) { + CalculateFlipSchedule( + mode_lib, ++ k, + HostVMInefficiencyFactor, + v->UrgentExtraLatency, + v->UrgentLatency, +- v->GPUVMMaxPageTableLevels, +- v->HostVMEnable, +- v->HostVMMaxNonCachedPageTableLevels, +- v->GPUVMEnable, +- v->HostVMMinPageSize, + v->PDEAndMetaPTEBytesFrame[k], + v->MetaRowByte[k], +- v->PixelPTEBytesPerRow[k], +- v->BandwidthAvailableForImmediateFlip, +- v->TotImmediateFlipBytes, +- v->SourcePixelFormat[k], +- v->HTotal[k] / v->PixelClock[k], +- v->VRatio[k], +- v->VRatioChroma[k], +- v->Tno_bw[k], +- v->DCCEnable[k], +- v->dpte_row_height[k], +- v->meta_row_height[k], +- v->dpte_row_height_chroma[k], +- v->meta_row_height_chroma[k], +- &v->DestinationLinesToRequestVMInImmediateFlip[k], +- &v->DestinationLinesToRequestRowInImmediateFlip[k], +- &v->final_flip_bw[k], +- &v->ImmediateFlipSupportedForPipe[k]); ++ v->PixelPTEBytesPerRow[k]); + } + + v->total_dcn_read_bw_with_flip = 0.0; +@@ -3624,61 +3584,43 @@ static void CalculateRowBandwidth( + + static void CalculateFlipSchedule( + struct display_mode_lib *mode_lib, ++ unsigned int k, + double HostVMInefficiencyFactor, + double UrgentExtraLatency, + double UrgentLatency, +- unsigned int GPUVMMaxPageTableLevels, +- bool HostVMEnable, +- unsigned int HostVMMaxNonCachedPageTableLevels, +- bool GPUVMEnable, +- double HostVMMinPageSize, + double PDEAndMetaPTEBytesPerFrame, + double MetaRowBytes, +- double DPTEBytesPerRow, +- double BandwidthAvailableForImmediateFlip, +- unsigned int TotImmediateFlipBytes, +- enum source_format_class SourcePixelFormat, +- double LineTime, +- double VRatio, +- double VRatioChroma, +- double Tno_bw, +- bool DCCEnable, +- unsigned int dpte_row_height, +- unsigned int meta_row_height, +- unsigned int dpte_row_height_chroma, +- unsigned int meta_row_height_chroma, +- double *DestinationLinesToRequestVMInImmediateFlip, +- double *DestinationLinesToRequestRowInImmediateFlip, +- double *final_flip_bw, +- bool *ImmediateFlipSupportedForPipe) ++ double DPTEBytesPerRow) + { ++ struct vba_vars_st *v = &mode_lib->vba; + double min_row_time = 0.0; + unsigned int HostVMDynamicLevelsTrips; + double TimeForFetchingMetaPTEImmediateFlip; + double TimeForFetchingRowInVBlankImmediateFlip; + double ImmediateFlipBW; ++ double LineTime = v->HTotal[k] / v->PixelClock[k]; + +- if (GPUVMEnable == true && HostVMEnable == true) { +- HostVMDynamicLevelsTrips = HostVMMaxNonCachedPageTableLevels; ++ if (v->GPUVMEnable == true && v->HostVMEnable == true) { ++ HostVMDynamicLevelsTrips = v->HostVMMaxNonCachedPageTableLevels; + } else { + HostVMDynamicLevelsTrips = 0; + } + +- if (GPUVMEnable == true || DCCEnable == true) { +- ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * BandwidthAvailableForImmediateFlip / TotImmediateFlipBytes; ++ if (v->GPUVMEnable == true || v->DCCEnable[k] == true) { ++ ImmediateFlipBW = (PDEAndMetaPTEBytesPerFrame + MetaRowBytes + DPTEBytesPerRow) * v->BandwidthAvailableForImmediateFlip / v->TotImmediateFlipBytes; + } + +- if (GPUVMEnable == true) { ++ if (v->GPUVMEnable == true) { + TimeForFetchingMetaPTEImmediateFlip = dml_max3( +- Tno_bw + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW, +- UrgentExtraLatency + UrgentLatency * (GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1), ++ v->Tno_bw[k] + PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / ImmediateFlipBW, ++ UrgentExtraLatency + UrgentLatency * (v->GPUVMMaxPageTableLevels * (HostVMDynamicLevelsTrips + 1) - 1), + LineTime / 4.0); + } else { + TimeForFetchingMetaPTEImmediateFlip = 0; + } + +- *DestinationLinesToRequestVMInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0; +- if ((GPUVMEnable == true || DCCEnable == true)) { ++ v->DestinationLinesToRequestVMInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingMetaPTEImmediateFlip / LineTime), 1) / 4.0; ++ if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) { + TimeForFetchingRowInVBlankImmediateFlip = dml_max3( + (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / ImmediateFlipBW, + UrgentLatency * (HostVMDynamicLevelsTrips + 1), +@@ -3687,54 +3629,54 @@ static void CalculateFlipSchedule( + TimeForFetchingRowInVBlankImmediateFlip = 0; + } + +- *DestinationLinesToRequestRowInImmediateFlip = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0; ++ v->DestinationLinesToRequestRowInImmediateFlip[k] = dml_ceil(4.0 * (TimeForFetchingRowInVBlankImmediateFlip / LineTime), 1) / 4.0; + +- if (GPUVMEnable == true) { +- *final_flip_bw = dml_max( +- PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (*DestinationLinesToRequestVMInImmediateFlip * LineTime), +- (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime)); +- } else if ((GPUVMEnable == true || DCCEnable == true)) { +- *final_flip_bw = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (*DestinationLinesToRequestRowInImmediateFlip * LineTime); ++ if (v->GPUVMEnable == true) { ++ v->final_flip_bw[k] = dml_max( ++ PDEAndMetaPTEBytesPerFrame * HostVMInefficiencyFactor / (v->DestinationLinesToRequestVMInImmediateFlip[k] * LineTime), ++ (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime)); ++ } else if ((v->GPUVMEnable == true || v->DCCEnable[k] == true)) { ++ v->final_flip_bw[k] = (MetaRowBytes + DPTEBytesPerRow * HostVMInefficiencyFactor) / (v->DestinationLinesToRequestRowInImmediateFlip[k] * LineTime); + } else { +- *final_flip_bw = 0; ++ v->final_flip_bw[k] = 0; + } + +- if (SourcePixelFormat == dm_420_8 || SourcePixelFormat == dm_420_10 || SourcePixelFormat == dm_rgbe_alpha) { +- if (GPUVMEnable == true && DCCEnable != true) { +- min_row_time = dml_min(dpte_row_height * LineTime / VRatio, dpte_row_height_chroma * LineTime / VRatioChroma); +- } else if (GPUVMEnable != true && DCCEnable == true) { +- min_row_time = dml_min(meta_row_height * LineTime / VRatio, meta_row_height_chroma * LineTime / VRatioChroma); ++ if (v->SourcePixelFormat[k] == dm_420_8 || v->SourcePixelFormat[k] == dm_420_10 || v->SourcePixelFormat[k] == dm_rgbe_alpha) { ++ if (v->GPUVMEnable == true && v->DCCEnable[k] != true) { ++ min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k]); ++ } else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) { ++ min_row_time = dml_min(v->meta_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]); + } else { + min_row_time = dml_min4( +- dpte_row_height * LineTime / VRatio, +- meta_row_height * LineTime / VRatio, +- dpte_row_height_chroma * LineTime / VRatioChroma, +- meta_row_height_chroma * LineTime / VRatioChroma); ++ v->dpte_row_height[k] * LineTime / v->VRatio[k], ++ v->meta_row_height[k] * LineTime / v->VRatio[k], ++ v->dpte_row_height_chroma[k] * LineTime / v->VRatioChroma[k], ++ v->meta_row_height_chroma[k] * LineTime / v->VRatioChroma[k]); + } + } else { +- if (GPUVMEnable == true && DCCEnable != true) { +- min_row_time = dpte_row_height * LineTime / VRatio; +- } else if (GPUVMEnable != true && DCCEnable == true) { +- min_row_time = meta_row_height * LineTime / VRatio; ++ if (v->GPUVMEnable == true && v->DCCEnable[k] != true) { ++ min_row_time = v->dpte_row_height[k] * LineTime / v->VRatio[k]; ++ } else if (v->GPUVMEnable != true && v->DCCEnable[k] == true) { ++ min_row_time = v->meta_row_height[k] * LineTime / v->VRatio[k]; + } else { +- min_row_time = dml_min(dpte_row_height * LineTime / VRatio, meta_row_height * LineTime / VRatio); ++ min_row_time = dml_min(v->dpte_row_height[k] * LineTime / v->VRatio[k], v->meta_row_height[k] * LineTime / v->VRatio[k]); + } + } + +- if (*DestinationLinesToRequestVMInImmediateFlip >= 32 || *DestinationLinesToRequestRowInImmediateFlip >= 16 ++ if (v->DestinationLinesToRequestVMInImmediateFlip[k] >= 32 || v->DestinationLinesToRequestRowInImmediateFlip[k] >= 16 + || TimeForFetchingMetaPTEImmediateFlip + 2 * TimeForFetchingRowInVBlankImmediateFlip > min_row_time) { +- *ImmediateFlipSupportedForPipe = false; ++ v->ImmediateFlipSupportedForPipe[k] = false; + } else { +- *ImmediateFlipSupportedForPipe = true; ++ v->ImmediateFlipSupportedForPipe[k] = true; + } + + #ifdef __DML_VBA_DEBUG__ +- dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestVMInImmediateFlip); +- dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, *DestinationLinesToRequestRowInImmediateFlip); ++ dml_print("DML::%s: DestinationLinesToRequestVMInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestVMInImmediateFlip[k]); ++ dml_print("DML::%s: DestinationLinesToRequestRowInImmediateFlip = %f\n", __func__, v->DestinationLinesToRequestRowInImmediateFlip[k]); + dml_print("DML::%s: TimeForFetchingMetaPTEImmediateFlip = %f\n", __func__, TimeForFetchingMetaPTEImmediateFlip); + dml_print("DML::%s: TimeForFetchingRowInVBlankImmediateFlip = %f\n", __func__, TimeForFetchingRowInVBlankImmediateFlip); + dml_print("DML::%s: min_row_time = %f\n", __func__, min_row_time); +- dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, *ImmediateFlipSupportedForPipe); ++ dml_print("DML::%s: ImmediateFlipSupportedForPipe = %d\n", __func__, v->ImmediateFlipSupportedForPipe[k]); + #endif + + } +@@ -5325,33 +5267,13 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l + for (k = 0; k < v->NumberOfActivePlanes; k++) { + CalculateFlipSchedule( + mode_lib, ++ k, + HostVMInefficiencyFactor, + v->ExtraLatency, + v->UrgLatency[i], +- v->GPUVMMaxPageTableLevels, +- v->HostVMEnable, +- v->HostVMMaxNonCachedPageTableLevels, +- v->GPUVMEnable, +- v->HostVMMinPageSize, + v->PDEAndMetaPTEBytesPerFrame[i][j][k], + v->MetaRowBytes[i][j][k], +- v->DPTEBytesPerRow[i][j][k], +- v->BandwidthAvailableForImmediateFlip, +- v->TotImmediateFlipBytes, +- v->SourcePixelFormat[k], +- v->HTotal[k] / v->PixelClock[k], +- v->VRatio[k], +- v->VRatioChroma[k], +- v->Tno_bw[k], +- v->DCCEnable[k], +- v->dpte_row_height[k], +- v->meta_row_height[k], +- v->dpte_row_height_chroma[k], +- v->meta_row_height_chroma[k], +- &v->DestinationLinesToRequestVMInImmediateFlip[k], +- &v->DestinationLinesToRequestRowInImmediateFlip[k], +- &v->final_flip_bw[k], +- &v->ImmediateFlipSupportedForPipe[k]); ++ v->DPTEBytesPerRow[i][j][k]); + } + v->total_dcn_read_bw_with_flip = 0.0; + for (k = 0; k < v->NumberOfActivePlanes; k++) { +-- +2.35.1 + diff --git a/queue-5.19/drm-amd-pm-disable-baco-entry-exit-completely-on-sev.patch b/queue-5.19/drm-amd-pm-disable-baco-entry-exit-completely-on-sev.patch new file mode 100644 index 00000000000..bbb980f7f11 --- /dev/null +++ b/queue-5.19/drm-amd-pm-disable-baco-entry-exit-completely-on-sev.patch @@ -0,0 +1,45 @@ +From 0f99b73ccbf4342a263023ef30a5092572b93143 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 20:31:36 +0800 +Subject: drm/amd/pm: disable BACO entry/exit completely on several sienna + cichlid cards + +From: Guchun Chen + +[ Upstream commit 7c6fb61a400bf3218c6504cb2d48858f98822c9d ] + +To avoid hardware intermittent failures. + +Signed-off-by: Guchun Chen +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +index 32bb6b1d9526..d13e455c8827 100644 +--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c ++++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +@@ -368,6 +368,17 @@ static void sienna_cichlid_check_bxco_support(struct smu_context *smu) + smu_baco->platform_support = + (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true : + false; ++ ++ /* ++ * Disable BACO entry/exit completely on below SKUs to ++ * avoid hardware intermittent failures. ++ */ ++ if (((adev->pdev->device == 0x73A1) && ++ (adev->pdev->revision == 0x00)) || ++ ((adev->pdev->device == 0x73BF) && ++ (adev->pdev->revision == 0xCF))) ++ smu_baco->platform_support = false; ++ + } + } + +-- +2.35.1 + diff --git a/queue-5.19/drm-amdgpu-add-hdp-remap-functionality-to-nbio-7.7.patch b/queue-5.19/drm-amdgpu-add-hdp-remap-functionality-to-nbio-7.7.patch new file mode 100644 index 00000000000..df0aab3f564 --- /dev/null +++ b/queue-5.19/drm-amdgpu-add-hdp-remap-functionality-to-nbio-7.7.patch @@ -0,0 +1,49 @@ +From 2e91ad686d8b5a3e92918aea35c30e50cc915a74 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 30 Aug 2022 11:08:09 -0400 +Subject: drm/amdgpu: add HDP remap functionality to nbio 7.7 + +From: Alex Deucher + +[ Upstream commit 8c5708d3da37b8c7c3c22c7e945b9a76a7c9539b ] + +Was missing before and would have resulted in a write to +a non-existant register. Normally APUs don't use HDP, but +other asics could use this code and APUs do use the HDP +when used in passthrough. + +Reviewed-by: Lijo Lazar +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c +index cdc0c9779848..6c1fd471a4c7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c ++++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c +@@ -28,6 +28,14 @@ + #include "nbio/nbio_7_7_0_sh_mask.h" + #include + ++static void nbio_v7_7_remap_hdp_registers(struct amdgpu_device *adev) ++{ ++ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL, ++ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL); ++ WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL, ++ adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL); ++} ++ + static u32 nbio_v7_7_get_rev_id(struct amdgpu_device *adev) + { + u32 tmp; +@@ -237,4 +245,5 @@ const struct amdgpu_nbio_funcs nbio_v7_7_funcs = { + .ih_doorbell_range = nbio_v7_7_ih_doorbell_range, + .ih_control = nbio_v7_7_ih_control, + .init_registers = nbio_v7_7_init_registers, ++ .remap_hdp_registers = nbio_v7_7_remap_hdp_registers, + }; +-- +2.35.1 + diff --git a/queue-5.19/drm-amdgpu-change-the-alignment-size-of-tmr-bo-to-1m.patch b/queue-5.19/drm-amdgpu-change-the-alignment-size-of-tmr-bo-to-1m.patch new file mode 100644 index 00000000000..e195f06cfbf --- /dev/null +++ b/queue-5.19/drm-amdgpu-change-the-alignment-size-of-tmr-bo-to-1m.patch @@ -0,0 +1,53 @@ +From 9a19bf5285135fc19a391863241edb0220009023 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 9 Sep 2022 11:06:50 +0800 +Subject: drm/amdgpu: change the alignment size of TMR BO to 1M + +From: Yang Wang + +[ Upstream commit 36de13fdb04abef3ee03ade5129ab146de63983b ] + +align TMR BO size TO tmr size is not necessary, +modify the size to 1M to avoid re-create BO fail +when serious VRAM fragmentation. + +v2: +add new macro PSP_TMR_ALIGNMENT for TMR BO alignment size + +Signed-off-by: Yang Wang +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- + drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + + 2 files changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +index b19bf0c3f373..79ce654bd3da 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +@@ -748,7 +748,7 @@ static int psp_tmr_init(struct psp_context *psp) + } + + pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; +- ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev), ++ ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT, + AMDGPU_GEM_DOMAIN_VRAM, + &psp->tmr_bo, &psp->tmr_mc_addr, pptr); + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +index e431f4994931..cd366c7f311f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +@@ -36,6 +36,7 @@ + #define PSP_CMD_BUFFER_SIZE 0x1000 + #define PSP_1_MEG 0x100000 + #define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000) ++#define PSP_TMR_ALIGNMENT 0x100000 + #define PSP_FW_NAME_LEN 0x24 + + enum psp_shared_mem_size { +-- +2.35.1 + diff --git a/queue-5.19/drm-amdgpu-skip-reset-error-status-for-psp-v13_0_0.patch b/queue-5.19/drm-amdgpu-skip-reset-error-status-for-psp-v13_0_0.patch new file mode 100644 index 00000000000..7169325f91e --- /dev/null +++ b/queue-5.19/drm-amdgpu-skip-reset-error-status-for-psp-v13_0_0.patch @@ -0,0 +1,36 @@ +From 70f0d01fb3799ae69e02691b6bc9c11541ebd887 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 7 Sep 2022 15:52:04 +0800 +Subject: drm/amdgpu: Skip reset error status for psp v13_0_0 + +From: Candice Li + +[ Upstream commit 86875d558b91cb46f43be112799c06ecce60ec1e ] + +No need to reset error status since only umc ras supported on psp v13_0_0. + +Signed-off-by: Candice Li +Reviewed-by: Hawking Zhang +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +index dac202ae864d..9193ca5d6fe7 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +@@ -1805,7 +1805,8 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev) + amdgpu_ras_query_error_status(adev, &info); + + if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && +- adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { ++ adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) && ++ adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) { + if (amdgpu_ras_reset_error_status(adev, info.head.block)) + dev_warn(adev->dev, "Failed to reset error counter and error status"); + } +-- +2.35.1 + diff --git a/queue-5.19/drm-amdgpu-use-dirty-framebuffer-helper.patch b/queue-5.19/drm-amdgpu-use-dirty-framebuffer-helper.patch new file mode 100644 index 00000000000..9a0d3ec6a34 --- /dev/null +++ b/queue-5.19/drm-amdgpu-use-dirty-framebuffer-helper.patch @@ -0,0 +1,44 @@ +From 997c58c19120386446e553a7d501b6744c1b6d31 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Sep 2022 15:01:49 -0400 +Subject: drm/amdgpu: use dirty framebuffer helper + +From: Hamza Mahfooz + +[ Upstream commit 66f99628eb24409cb8feb5061f78283c8b65f820 ] + +Currently, we aren't handling DRM_IOCTL_MODE_DIRTYFB. So, use +drm_atomic_helper_dirtyfb() as the dirty callback in the amdgpu_fb_funcs +struct. + +Signed-off-by: Hamza Mahfooz +Acked-by: Alex Deucher +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +index 4dfd6724b3ca..3451147beda3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +@@ -35,6 +35,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -493,6 +494,7 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, + static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { + .destroy = drm_gem_fb_destroy, + .create_handle = drm_gem_fb_create_handle, ++ .dirty = drm_atomic_helper_dirtyfb, + }; + + uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, +-- +2.35.1 + diff --git a/queue-5.19/drm-gma500-fix-bug-sleeping-function-called-from-inv.patch b/queue-5.19/drm-gma500-fix-bug-sleeping-function-called-from-inv.patch new file mode 100644 index 00000000000..137abd8d221 --- /dev/null +++ b/queue-5.19/drm-gma500-fix-bug-sleeping-function-called-from-inv.patch @@ -0,0 +1,106 @@ +From be0d60ba10000b7f6e37fe07270a500c0195c1f8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Sep 2022 22:38:50 +0200 +Subject: drm/gma500: Fix BUG: sleeping function called from invalid context + errors + +From: Hans de Goede + +[ Upstream commit 63e37a79f7bd939314997e29c2f5a9f0ef184281 ] + +gma_crtc_page_flip() was holding the event_lock spinlock while calling +crtc_funcs->mode_set_base() which takes ww_mutex. + +The only reason to hold event_lock is to clear gma_crtc->page_flip_event +on mode_set_base() errors. + +Instead unlock it after setting gma_crtc->page_flip_event and on +errors re-take the lock and clear gma_crtc->page_flip_event it +it is still set. + +This fixes the following WARN/stacktrace: + +[ 512.122953] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:870 +[ 512.123004] in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 1253, name: gnome-shell +[ 512.123031] preempt_count: 1, expected: 0 +[ 512.123048] RCU nest depth: 0, expected: 0 +[ 512.123066] INFO: lockdep is turned off. +[ 512.123080] irq event stamp: 0 +[ 512.123094] hardirqs last enabled at (0): [<0000000000000000>] 0x0 +[ 512.123134] hardirqs last disabled at (0): [] copy_process+0x9fc/0x1de0 +[ 512.123176] softirqs last enabled at (0): [] copy_process+0x9fc/0x1de0 +[ 512.123207] softirqs last disabled at (0): [<0000000000000000>] 0x0 +[ 512.123233] Preemption disabled at: +[ 512.123241] [<0000000000000000>] 0x0 +[ 512.123275] CPU: 3 PID: 1253 Comm: gnome-shell Tainted: G W 5.19.0+ #1 +[ 512.123304] Hardware name: Packard Bell dot s/SJE01_CT, BIOS V1.10 07/23/2013 +[ 512.123323] Call Trace: +[ 512.123346] +[ 512.123370] dump_stack_lvl+0x5b/0x77 +[ 512.123412] __might_resched.cold+0xff/0x13a +[ 512.123458] ww_mutex_lock+0x1e/0xa0 +[ 512.123495] psb_gem_pin+0x2c/0x150 [gma500_gfx] +[ 512.123601] gma_pipe_set_base+0x76/0x240 [gma500_gfx] +[ 512.123708] gma_crtc_page_flip+0x95/0x130 [gma500_gfx] +[ 512.123808] drm_mode_page_flip_ioctl+0x57d/0x5d0 +[ 512.123897] ? drm_mode_cursor2_ioctl+0x10/0x10 +[ 512.123936] drm_ioctl_kernel+0xa1/0x150 +[ 512.123984] drm_ioctl+0x21f/0x420 +[ 512.124025] ? drm_mode_cursor2_ioctl+0x10/0x10 +[ 512.124070] ? rcu_read_lock_bh_held+0xb/0x60 +[ 512.124104] ? lock_release+0x1ef/0x2d0 +[ 512.124161] __x64_sys_ioctl+0x8d/0xd0 +[ 512.124203] do_syscall_64+0x58/0x80 +[ 512.124239] ? do_syscall_64+0x67/0x80 +[ 512.124267] ? trace_hardirqs_on_prepare+0x55/0xe0 +[ 512.124300] ? do_syscall_64+0x67/0x80 +[ 512.124340] ? rcu_read_lock_sched_held+0x10/0x80 +[ 512.124377] entry_SYSCALL_64_after_hwframe+0x63/0xcd +[ 512.124411] RIP: 0033:0x7fcc4a70740f +[ 512.124442] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <89> c2 3d 00 f0 ff ff 77 18 48 8b 44 24 18 64 48 2b 04 25 28 00 00 +[ 512.124470] RSP: 002b:00007ffda73f5390 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 +[ 512.124503] RAX: ffffffffffffffda RBX: 000055cc9e474500 RCX: 00007fcc4a70740f +[ 512.124524] RDX: 00007ffda73f5420 RSI: 00000000c01864b0 RDI: 0000000000000009 +[ 512.124544] RBP: 00007ffda73f5420 R08: 000055cc9c0b0cb0 R09: 0000000000000034 +[ 512.124564] R10: 0000000000000000 R11: 0000000000000246 R12: 00000000c01864b0 +[ 512.124584] R13: 0000000000000009 R14: 000055cc9df484d0 R15: 000055cc9af5d0c0 +[ 512.124647] + +Signed-off-by: Hans de Goede +Signed-off-by: Patrik Jakobsson +Link: https://patchwork.freedesktop.org/patch/msgid/20220906203852.527663-2-hdegoede@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/gma500/gma_display.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/gma500/gma_display.c b/drivers/gpu/drm/gma500/gma_display.c +index 34ec3fca09ba..12287c9bb4d8 100644 +--- a/drivers/gpu/drm/gma500/gma_display.c ++++ b/drivers/gpu/drm/gma500/gma_display.c +@@ -531,15 +531,18 @@ int gma_crtc_page_flip(struct drm_crtc *crtc, + WARN_ON(drm_crtc_vblank_get(crtc) != 0); + + gma_crtc->page_flip_event = event; ++ spin_unlock_irqrestore(&dev->event_lock, flags); + + /* Call this locked if we want an event at vblank interrupt. */ + ret = crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y, old_fb); + if (ret) { +- gma_crtc->page_flip_event = NULL; +- drm_crtc_vblank_put(crtc); ++ spin_lock_irqsave(&dev->event_lock, flags); ++ if (gma_crtc->page_flip_event) { ++ gma_crtc->page_flip_event = NULL; ++ drm_crtc_vblank_put(crtc); ++ } ++ spin_unlock_irqrestore(&dev->event_lock, flags); + } +- +- spin_unlock_irqrestore(&dev->event_lock, flags); + } else { + ret = crtc_funcs->mode_set_base(crtc, crtc->x, crtc->y, old_fb); + } +-- +2.35.1 + diff --git a/queue-5.19/drm-gma500-fix-vblank-irqs-not-working-after-suspend.patch b/queue-5.19/drm-gma500-fix-vblank-irqs-not-working-after-suspend.patch new file mode 100644 index 00000000000..de6c8835b8b --- /dev/null +++ b/queue-5.19/drm-gma500-fix-vblank-irqs-not-working-after-suspend.patch @@ -0,0 +1,206 @@ +From 8315e3dc8912ef4745be22d077e2a0349ce140f8 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Sep 2022 22:38:52 +0200 +Subject: drm/gma500: Fix (vblank) IRQs not working after suspend/resume + +From: Hans de Goede + +[ Upstream commit 235fdbc32d559db21e580f85035c59372704f09e ] + +Fix gnome-shell (and other page-flip users) hanging after suspend/resume +because of the gma500's IRQs not working. + +This fixes 2 problems with the IRQ handling: + +1. gma_power_off() calls gma_irq_uninstall() which does a free_irq(), but + gma_power_on() called gma_irq_preinstall() + gma_irq_postinstall() which + do not call request_irq. Replace the pre- + post-install calls with + gma_irq_install() which does prep + request + post. + +2. After fixing 1. IRQs still do not work on a Packard Bell Dot SC (Intel + Atom N2600, cedarview) netbook. + + Cederview uses MSI interrupts and it seems that the BIOS re-configures + things back to normal APIC based interrupts during S3 suspend. There is + some MSI PCI-config registers save/restore code which tries to deal with + this, but on the Packard Bell Dot SC this is not sufficient to restore + MSI IRQ functionality after a suspend/resume. + + Replace the PCI-config registers save/restore with pci_disable_msi() on + suspend + pci_enable_msi() on resume. Fixing e.g. gnome-shell hanging. + +Signed-off-by: Hans de Goede +Signed-off-by: Patrik Jakobsson +Link: https://patchwork.freedesktop.org/patch/msgid/20220906203852.527663-4-hdegoede@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/gma500/cdv_device.c | 4 +--- + drivers/gpu/drm/gma500/oaktrail_device.c | 5 +---- + drivers/gpu/drm/gma500/power.c | 8 +------- + drivers/gpu/drm/gma500/psb_drv.c | 2 +- + drivers/gpu/drm/gma500/psb_drv.h | 5 +---- + drivers/gpu/drm/gma500/psb_irq.c | 15 ++++++++++++--- + drivers/gpu/drm/gma500/psb_irq.h | 2 +- + 7 files changed, 18 insertions(+), 23 deletions(-) + +diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c +index dd32b484dd82..ce96234f3df2 100644 +--- a/drivers/gpu/drm/gma500/cdv_device.c ++++ b/drivers/gpu/drm/gma500/cdv_device.c +@@ -581,11 +581,9 @@ static const struct psb_offset cdv_regmap[2] = { + static int cdv_chip_setup(struct drm_device *dev) + { + struct drm_psb_private *dev_priv = to_drm_psb_private(dev); +- struct pci_dev *pdev = to_pci_dev(dev->dev); + INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func); + +- if (pci_enable_msi(pdev)) +- dev_warn(dev->dev, "Enabling MSI failed!\n"); ++ dev_priv->use_msi = true; + dev_priv->regmap = cdv_regmap; + gma_get_core_freq(dev); + psb_intel_opregion_init(dev); +diff --git a/drivers/gpu/drm/gma500/oaktrail_device.c b/drivers/gpu/drm/gma500/oaktrail_device.c +index 5923a9c89312..f90e628cb482 100644 +--- a/drivers/gpu/drm/gma500/oaktrail_device.c ++++ b/drivers/gpu/drm/gma500/oaktrail_device.c +@@ -501,12 +501,9 @@ static const struct psb_offset oaktrail_regmap[2] = { + static int oaktrail_chip_setup(struct drm_device *dev) + { + struct drm_psb_private *dev_priv = to_drm_psb_private(dev); +- struct pci_dev *pdev = to_pci_dev(dev->dev); + int ret; + +- if (pci_enable_msi(pdev)) +- dev_warn(dev->dev, "Enabling MSI failed!\n"); +- ++ dev_priv->use_msi = true; + dev_priv->regmap = oaktrail_regmap; + + ret = mid_chip_setup(dev); +diff --git a/drivers/gpu/drm/gma500/power.c b/drivers/gpu/drm/gma500/power.c +index b91de6d36e41..66873085d450 100644 +--- a/drivers/gpu/drm/gma500/power.c ++++ b/drivers/gpu/drm/gma500/power.c +@@ -139,8 +139,6 @@ static void gma_suspend_pci(struct pci_dev *pdev) + dev_priv->regs.saveBSM = bsm; + pci_read_config_dword(pdev, 0xFC, &vbt); + dev_priv->regs.saveVBT = vbt; +- pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr); +- pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data); + + pci_disable_device(pdev); + pci_set_power_state(pdev, PCI_D3hot); +@@ -168,9 +166,6 @@ static bool gma_resume_pci(struct pci_dev *pdev) + pci_restore_state(pdev); + pci_write_config_dword(pdev, 0x5c, dev_priv->regs.saveBSM); + pci_write_config_dword(pdev, 0xFC, dev_priv->regs.saveVBT); +- /* restoring MSI address and data in PCIx space */ +- pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr); +- pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data); + ret = pci_enable_device(pdev); + + if (ret != 0) +@@ -223,8 +218,7 @@ int gma_power_resume(struct device *_dev) + mutex_lock(&power_mutex); + gma_resume_pci(pdev); + gma_resume_display(pdev); +- gma_irq_preinstall(dev); +- gma_irq_postinstall(dev); ++ gma_irq_install(dev); + mutex_unlock(&power_mutex); + return 0; + } +diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c +index 1d8744f3e702..54e756b48606 100644 +--- a/drivers/gpu/drm/gma500/psb_drv.c ++++ b/drivers/gpu/drm/gma500/psb_drv.c +@@ -383,7 +383,7 @@ static int psb_driver_load(struct drm_device *dev, unsigned long flags) + PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R); + spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); + +- gma_irq_install(dev, pdev->irq); ++ gma_irq_install(dev); + + dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ + +diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h +index 0ddfec1a0851..4c3fc5eaf6ad 100644 +--- a/drivers/gpu/drm/gma500/psb_drv.h ++++ b/drivers/gpu/drm/gma500/psb_drv.h +@@ -490,6 +490,7 @@ struct drm_psb_private { + int rpm_enabled; + + /* MID specific */ ++ bool use_msi; + bool has_gct; + struct oaktrail_gct_data gct_data; + +@@ -499,10 +500,6 @@ struct drm_psb_private { + /* Register state */ + struct psb_save_area regs; + +- /* MSI reg save */ +- uint32_t msi_addr; +- uint32_t msi_data; +- + /* Hotplug handling */ + struct work_struct hotplug_work; + +diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c +index e6e6d61bbeab..038f18ed0a95 100644 +--- a/drivers/gpu/drm/gma500/psb_irq.c ++++ b/drivers/gpu/drm/gma500/psb_irq.c +@@ -316,17 +316,24 @@ void gma_irq_postinstall(struct drm_device *dev) + spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); + } + +-int gma_irq_install(struct drm_device *dev, unsigned int irq) ++int gma_irq_install(struct drm_device *dev) + { ++ struct drm_psb_private *dev_priv = to_drm_psb_private(dev); ++ struct pci_dev *pdev = to_pci_dev(dev->dev); + int ret; + +- if (irq == IRQ_NOTCONNECTED) ++ if (dev_priv->use_msi && pci_enable_msi(pdev)) { ++ dev_warn(dev->dev, "Enabling MSI failed!\n"); ++ dev_priv->use_msi = false; ++ } ++ ++ if (pdev->irq == IRQ_NOTCONNECTED) + return -ENOTCONN; + + gma_irq_preinstall(dev); + + /* PCI devices require shared interrupts. */ +- ret = request_irq(irq, gma_irq_handler, IRQF_SHARED, dev->driver->name, dev); ++ ret = request_irq(pdev->irq, gma_irq_handler, IRQF_SHARED, dev->driver->name, dev); + if (ret) + return ret; + +@@ -369,6 +376,8 @@ void gma_irq_uninstall(struct drm_device *dev) + spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags); + + free_irq(pdev->irq, dev); ++ if (dev_priv->use_msi) ++ pci_disable_msi(pdev); + } + + int gma_crtc_enable_vblank(struct drm_crtc *crtc) +diff --git a/drivers/gpu/drm/gma500/psb_irq.h b/drivers/gpu/drm/gma500/psb_irq.h +index b51e395194ff..7648f69824a5 100644 +--- a/drivers/gpu/drm/gma500/psb_irq.h ++++ b/drivers/gpu/drm/gma500/psb_irq.h +@@ -17,7 +17,7 @@ struct drm_device; + + void gma_irq_preinstall(struct drm_device *dev); + void gma_irq_postinstall(struct drm_device *dev); +-int gma_irq_install(struct drm_device *dev, unsigned int irq); ++int gma_irq_install(struct drm_device *dev); + void gma_irq_uninstall(struct drm_device *dev); + + int gma_crtc_enable_vblank(struct drm_crtc *crtc); +-- +2.35.1 + diff --git a/queue-5.19/drm-gma500-fix-warn_on-lock-magic-lock-error.patch b/queue-5.19/drm-gma500-fix-warn_on-lock-magic-lock-error.patch new file mode 100644 index 00000000000..dc6e4e0b643 --- /dev/null +++ b/queue-5.19/drm-gma500-fix-warn_on-lock-magic-lock-error.patch @@ -0,0 +1,107 @@ +From b834fda34fddafd279de6e9e341637a7de8a8e59 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 6 Sep 2022 22:38:51 +0200 +Subject: drm/gma500: Fix WARN_ON(lock->magic != lock) error + +From: Hans de Goede + +[ Upstream commit b6f25c3b94f2aadbf5cbef954db4073614943d74 ] + +psb_gem_unpin() calls dma_resv_lock() but the underlying ww_mutex +gets destroyed by drm_gem_object_release() move the +drm_gem_object_release() call in psb_gem_free_object() to after +the unpin to fix the below warning: + +[ 79.693962] ------------[ cut here ]------------ +[ 79.693992] DEBUG_LOCKS_WARN_ON(lock->magic != lock) +[ 79.694015] WARNING: CPU: 0 PID: 240 at kernel/locking/mutex.c:582 __ww_mutex_lock.constprop.0+0x569/0xfb0 +[ 79.694052] Modules linked in: rfcomm snd_seq_dummy snd_hrtimer qrtr bnep ath9k ath9k_common ath9k_hw snd_hda_codec_realtek snd_hda_codec_generic ledtrig_audio snd_hda_codec_hdmi snd_hda_intel ath3k snd_intel_dspcfg mac80211 snd_intel_sdw_acpi btusb snd_hda_codec btrtl btbcm btintel btmtk bluetooth at24 snd_hda_core snd_hwdep uvcvideo snd_seq libarc4 videobuf2_vmalloc ath videobuf2_memops videobuf2_v4l2 videobuf2_common snd_seq_device videodev acer_wmi intel_powerclamp coretemp mc snd_pcm joydev sparse_keymap ecdh_generic pcspkr wmi_bmof cfg80211 i2c_i801 i2c_smbus snd_timer snd r8169 rfkill lpc_ich soundcore acpi_cpufreq zram rtsx_pci_sdmmc mmc_core serio_raw rtsx_pci gma500_gfx(E) video wmi ip6_tables ip_tables i2c_dev fuse +[ 79.694436] CPU: 0 PID: 240 Comm: plymouthd Tainted: G W E 6.0.0-rc3+ #490 +[ 79.694457] Hardware name: Packard Bell dot s/SJE01_CT, BIOS V1.10 07/23/2013 +[ 79.694469] RIP: 0010:__ww_mutex_lock.constprop.0+0x569/0xfb0 +[ 79.694496] Code: ff 85 c0 0f 84 15 fb ff ff 8b 05 ca 3c 11 01 85 c0 0f 85 07 fb ff ff 48 c7 c6 30 cb 84 aa 48 c7 c7 a3 e1 82 aa e8 ac 29 f8 ff <0f> 0b e9 ed fa ff ff e8 5b 83 8a ff 85 c0 74 10 44 8b 0d 98 3c 11 +[ 79.694513] RSP: 0018:ffffad1dc048bbe0 EFLAGS: 00010282 +[ 79.694623] RAX: 0000000000000028 RBX: 0000000000000000 RCX: 0000000000000000 +[ 79.694636] RDX: 0000000000000001 RSI: ffffffffaa8b0ffc RDI: 00000000ffffffff +[ 79.694650] RBP: ffffad1dc048bc80 R08: 0000000000000000 R09: ffffad1dc048ba90 +[ 79.694662] R10: 0000000000000003 R11: ffffffffaad62fe8 R12: ffff9ff302103138 +[ 79.694675] R13: ffff9ff306ec8000 R14: ffff9ff307779078 R15: ffff9ff3014c0270 +[ 79.694690] FS: 00007ff1cccf1740(0000) GS:ffff9ff3bc200000(0000) knlGS:0000000000000000 +[ 79.694705] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +[ 79.694719] CR2: 0000559ecbcb4420 CR3: 0000000013210000 CR4: 00000000000006f0 +[ 79.694734] Call Trace: +[ 79.694749] +[ 79.694761] ? __schedule+0x47f/0x1670 +[ 79.694796] ? psb_gem_unpin+0x27/0x1a0 [gma500_gfx] +[ 79.694830] ? lock_is_held_type+0xe3/0x140 +[ 79.694864] ? ww_mutex_lock+0x38/0xa0 +[ 79.694885] ? __cond_resched+0x1c/0x30 +[ 79.694902] ww_mutex_lock+0x38/0xa0 +[ 79.694925] psb_gem_unpin+0x27/0x1a0 [gma500_gfx] +[ 79.694964] psb_gem_unpin+0x199/0x1a0 [gma500_gfx] +[ 79.694996] drm_gem_object_release_handle+0x50/0x60 +[ 79.695020] ? drm_gem_object_handle_put_unlocked+0xf0/0xf0 +[ 79.695042] idr_for_each+0x4b/0xb0 +[ 79.695066] ? _raw_spin_unlock_irqrestore+0x30/0x60 +[ 79.695095] drm_gem_release+0x1c/0x30 +[ 79.695118] drm_file_free.part.0+0x1ea/0x260 +[ 79.695150] drm_release+0x6a/0x120 +[ 79.695175] __fput+0x9f/0x260 +[ 79.695203] task_work_run+0x59/0xa0 +[ 79.695227] do_exit+0x387/0xbe0 +[ 79.695250] ? seqcount_lockdep_reader_access.constprop.0+0x82/0x90 +[ 79.695275] ? lockdep_hardirqs_on+0x7d/0x100 +[ 79.695304] do_group_exit+0x33/0xb0 +[ 79.695331] __x64_sys_exit_group+0x14/0x20 +[ 79.695353] do_syscall_64+0x58/0x80 +[ 79.695376] ? up_read+0x17/0x20 +[ 79.695401] ? lock_is_held_type+0xe3/0x140 +[ 79.695429] ? asm_exc_page_fault+0x22/0x30 +[ 79.695450] ? lockdep_hardirqs_on+0x7d/0x100 +[ 79.695473] entry_SYSCALL_64_after_hwframe+0x63/0xcd +[ 79.695493] RIP: 0033:0x7ff1ccefe3f1 +[ 79.695516] Code: Unable to access opcode bytes at RIP 0x7ff1ccefe3c7. +[ 79.695607] RSP: 002b:00007ffed4413378 EFLAGS: 00000246 ORIG_RAX: 00000000000000e7 +[ 79.695629] RAX: ffffffffffffffda RBX: 00007ff1cd0159e0 RCX: 00007ff1ccefe3f1 +[ 79.695644] RDX: 000000000000003c RSI: 00000000000000e7 RDI: 0000000000000000 +[ 79.695656] RBP: 0000000000000000 R08: ffffffffffffff80 R09: 00007ff1cd020b20 +[ 79.695671] R10: 0000000000000000 R11: 0000000000000246 R12: 00007ff1cd0159e0 +[ 79.695684] R13: 0000000000000000 R14: 00007ff1cd01aee8 R15: 00007ff1cd01af00 +[ 79.695733] +[ 79.695746] irq event stamp: 725979 +[ 79.695757] hardirqs last enabled at (725979): [] finish_task_switch.isra.0+0xe4/0x3f0 +[ 79.695780] hardirqs last disabled at (725978): [] __schedule+0xdd3/0x1670 +[ 79.695803] softirqs last enabled at (725974): [] __irq_exit_rcu+0xed/0x160 +[ 79.695825] softirqs last disabled at (725969): [] __irq_exit_rcu+0xed/0x160 +[ 79.695845] ---[ end trace 0000000000000000 ]--- + +Signed-off-by: Hans de Goede +Signed-off-by: Patrik Jakobsson +Link: https://patchwork.freedesktop.org/patch/msgid/20220906203852.527663-3-hdegoede@redhat.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/gma500/gem.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/gma500/gem.c b/drivers/gpu/drm/gma500/gem.c +index dffe37490206..4b7627a72637 100644 +--- a/drivers/gpu/drm/gma500/gem.c ++++ b/drivers/gpu/drm/gma500/gem.c +@@ -112,12 +112,12 @@ static void psb_gem_free_object(struct drm_gem_object *obj) + { + struct psb_gem_object *pobj = to_psb_gem_object(obj); + +- drm_gem_object_release(obj); +- + /* Undo the mmap pin if we are destroying the object */ + if (pobj->mmapping) + psb_gem_unpin(pobj); + ++ drm_gem_object_release(obj); ++ + WARN_ON(pobj->in_gart && !pobj->stolen); + + release_resource(&pobj->resource); +-- +2.35.1 + diff --git a/queue-5.19/drm-rockchip-fix-return-type-of-cdn_dp_connector_mod.patch b/queue-5.19/drm-rockchip-fix-return-type-of-cdn_dp_connector_mod.patch new file mode 100644 index 00000000000..dcc37ca931e --- /dev/null +++ b/queue-5.19/drm-rockchip-fix-return-type-of-cdn_dp_connector_mod.patch @@ -0,0 +1,51 @@ +From 805434802f123750acfff2097b8dff4028d0777e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 13:55:55 -0700 +Subject: drm/rockchip: Fix return type of cdn_dp_connector_mode_valid + +From: Nathan Huckleberry + +[ Upstream commit b0b9408f132623dc88e78adb5282f74e4b64bb57 ] + +The mode_valid field in drm_connector_helper_funcs is expected to be of +type: +enum drm_mode_status (* mode_valid) (struct drm_connector *connector, + struct drm_display_mode *mode); + +The mismatched return type breaks forward edge kCFI since the underlying +function definition does not match the function hook definition. + +The return type of cdn_dp_connector_mode_valid should be changed from +int to enum drm_mode_status. + +Reported-by: Dan Carpenter +Link: https://github.com/ClangBuiltLinux/linux/issues/1703 +Cc: llvm@lists.linux.dev +Signed-off-by: Nathan Huckleberry +Reviewed-by: Nathan Chancellor +Signed-off-by: Heiko Stuebner +Link: https://patchwork.freedesktop.org/patch/msgid/20220913205555.155149-1-nhuck@google.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/rockchip/cdn-dp-core.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c +index c204e9b95c1f..518ee13b1d6f 100644 +--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c ++++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c +@@ -283,8 +283,9 @@ static int cdn_dp_connector_get_modes(struct drm_connector *connector) + return ret; + } + +-static int cdn_dp_connector_mode_valid(struct drm_connector *connector, +- struct drm_display_mode *mode) ++static enum drm_mode_status ++cdn_dp_connector_mode_valid(struct drm_connector *connector, ++ struct drm_display_mode *mode) + { + struct cdn_dp_device *dp = connector_to_dp(connector); + struct drm_display_info *display_info = &dp->connector.display_info; +-- +2.35.1 + diff --git a/queue-5.19/gpio-ixp4xx-make-irqchip-immutable.patch b/queue-5.19/gpio-ixp4xx-make-irqchip-immutable.patch new file mode 100644 index 00000000000..cfb177b8095 --- /dev/null +++ b/queue-5.19/gpio-ixp4xx-make-irqchip-immutable.patch @@ -0,0 +1,82 @@ +From 6278c1c2b15db598569ea838bc4b22546b52943d Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 11 Sep 2022 21:07:51 +0200 +Subject: gpio: ixp4xx: Make irqchip immutable + +From: Linus Walleij + +[ Upstream commit 94e9bc73d85aa6ecfe249e985ff57abe0ab35f34 ] + +This turns the IXP4xx GPIO irqchip into an immutable +irqchip, a bit different from the standard template due +to being hierarchical. + +Tested on the IXP4xx which uses drivers/ata/pata_ixp4xx_cf.c +for a rootfs on compact flash with IRQs from this GPIO +block to the CF ATA controller. + +Cc: Marc Zyngier +Signed-off-by: Linus Walleij +Acked-by: Marc Zyngier +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpio-ixp4xx.c | 17 ++++++++++++++--- + 1 file changed, 14 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpio/gpio-ixp4xx.c b/drivers/gpio/gpio-ixp4xx.c +index 312309be0287..56656fb519f8 100644 +--- a/drivers/gpio/gpio-ixp4xx.c ++++ b/drivers/gpio/gpio-ixp4xx.c +@@ -63,6 +63,14 @@ static void ixp4xx_gpio_irq_ack(struct irq_data *d) + __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); + } + ++static void ixp4xx_gpio_mask_irq(struct irq_data *d) ++{ ++ struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ ++ irq_chip_mask_parent(d); ++ gpiochip_disable_irq(gc, d->hwirq); ++} ++ + static void ixp4xx_gpio_irq_unmask(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); +@@ -72,6 +80,7 @@ static void ixp4xx_gpio_irq_unmask(struct irq_data *d) + if (!(g->irq_edge & BIT(d->hwirq))) + ixp4xx_gpio_irq_ack(d); + ++ gpiochip_enable_irq(gc, d->hwirq); + irq_chip_unmask_parent(d); + } + +@@ -149,12 +158,14 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type) + return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); + } + +-static struct irq_chip ixp4xx_gpio_irqchip = { ++static const struct irq_chip ixp4xx_gpio_irqchip = { + .name = "IXP4GPIO", + .irq_ack = ixp4xx_gpio_irq_ack, +- .irq_mask = irq_chip_mask_parent, ++ .irq_mask = ixp4xx_gpio_mask_irq, + .irq_unmask = ixp4xx_gpio_irq_unmask, + .irq_set_type = ixp4xx_gpio_irq_set_type, ++ .flags = IRQCHIP_IMMUTABLE, ++ GPIOCHIP_IRQ_RESOURCE_HELPERS, + }; + + static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, +@@ -263,7 +274,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev) + g->gc.owner = THIS_MODULE; + + girq = &g->gc.irq; +- girq->chip = &ixp4xx_gpio_irqchip; ++ gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip); + girq->fwnode = g->fwnode; + girq->parent_domain = parent; + girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq; +-- +2.35.1 + diff --git a/queue-5.19/gpio-mt7621-make-the-irqchip-immutable.patch b/queue-5.19/gpio-mt7621-make-the-irqchip-immutable.patch new file mode 100644 index 00000000000..c267e5c1b92 --- /dev/null +++ b/queue-5.19/gpio-mt7621-make-the-irqchip-immutable.patch @@ -0,0 +1,94 @@ +From 915f1c8afa92790e85e21e4221ebf4920ef83e55 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 13 Sep 2022 18:46:38 +0200 +Subject: gpio: mt7621: Make the irqchip immutable +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Sergio Paracuellos + +[ Upstream commit 09eed5a1ed3c752892663976837eb4244c2f1984 ] + +Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as +immutable") added a warning to indicate if the gpiolib is altering the +internals of irqchips. Following this change the following warnings +are now observed for the mt7621 driver: + +gpio gpiochip0: (1e000600.gpio-bank0): not an immutable chip, please consider fixing it! +gpio gpiochip1: (1e000600.gpio-bank1): not an immutable chip, please consider fixing it! +gpio gpiochip2: (1e000600.gpio-bank2): not an immutable chip, please consider fixing it! + +Fix this by making the irqchip in the mt7621 driver immutable. + +Tested-by: Arınç ÜNAL +Signed-off-by: Sergio Paracuellos +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpio-mt7621.c | 21 +++++++++++++++------ + 1 file changed, 15 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpio/gpio-mt7621.c b/drivers/gpio/gpio-mt7621.c +index d8a26e503ca5..f163f5ca857b 100644 +--- a/drivers/gpio/gpio-mt7621.c ++++ b/drivers/gpio/gpio-mt7621.c +@@ -112,6 +112,8 @@ mediatek_gpio_irq_unmask(struct irq_data *d) + unsigned long flags; + u32 rise, fall, high, low; + ++ gpiochip_enable_irq(gc, d->hwirq); ++ + spin_lock_irqsave(&rg->lock, flags); + rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); + fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); +@@ -143,6 +145,8 @@ mediatek_gpio_irq_mask(struct irq_data *d) + mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); + mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); + spin_unlock_irqrestore(&rg->lock, flags); ++ ++ gpiochip_disable_irq(gc, d->hwirq); + } + + static int +@@ -204,6 +208,16 @@ mediatek_gpio_xlate(struct gpio_chip *chip, + return gpio % MTK_BANK_WIDTH; + } + ++static const struct irq_chip mt7621_irq_chip = { ++ .name = "mt7621-gpio", ++ .irq_mask_ack = mediatek_gpio_irq_mask, ++ .irq_mask = mediatek_gpio_irq_mask, ++ .irq_unmask = mediatek_gpio_irq_unmask, ++ .irq_set_type = mediatek_gpio_irq_type, ++ .flags = IRQCHIP_IMMUTABLE, ++ GPIOCHIP_IRQ_RESOURCE_HELPERS, ++}; ++ + static int + mediatek_gpio_bank_probe(struct device *dev, int bank) + { +@@ -238,11 +252,6 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) + return -ENOMEM; + + rg->chip.offset = bank * MTK_BANK_WIDTH; +- rg->irq_chip.name = dev_name(dev); +- rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask; +- rg->irq_chip.irq_mask = mediatek_gpio_irq_mask; +- rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask; +- rg->irq_chip.irq_set_type = mediatek_gpio_irq_type; + + if (mtk->gpio_irq) { + struct gpio_irq_chip *girq; +@@ -262,7 +271,7 @@ mediatek_gpio_bank_probe(struct device *dev, int bank) + } + + girq = &rg->chip.irq; +- girq->chip = &rg->irq_chip; ++ gpio_irq_chip_set_chip(girq, &mt7621_irq_chip); + /* This will let us handle the parent IRQ in the driver */ + girq->parent_handler = NULL; + girq->num_parents = 0; +-- +2.35.1 + diff --git a/queue-5.19/series b/queue-5.19/series index 0f74c6872d9..4b746ddc700 100644 --- a/queue-5.19/series +++ b/queue-5.19/series @@ -168,3 +168,19 @@ drm-i915-display-fix-handling-of-enable_psr-parameter.patch blk-mq-fix-error-handling-in-__blk_mq_alloc_disk.patch block-call-blk_mq_exit_queue-from-disk_release-for-never-added-disks.patch block-do-not-call-blk_put_queue-if-gendisk-allocation-fails.patch +drivers-hv-never-allocate-anything-besides-framebuff.patch +drm-gma500-fix-bug-sleeping-function-called-from-inv.patch +drm-gma500-fix-warn_on-lock-magic-lock-error.patch +drm-gma500-fix-vblank-irqs-not-working-after-suspend.patch +gpio-ixp4xx-make-irqchip-immutable.patch +drm-amd-pm-disable-baco-entry-exit-completely-on-sev.patch +drm-amdgpu-use-dirty-framebuffer-helper.patch +drm-amdgpu-change-the-alignment-size-of-tmr-bo-to-1m.patch +drm-amdgpu-add-hdp-remap-functionality-to-nbio-7.7.patch +drm-amdgpu-skip-reset-error-status-for-psp-v13_0_0.patch +drm-amd-display-limit-user-regamma-to-a-valid-value.patch +drm-amd-display-reduce-number-of-arguments-of-dml31-.patch +drm-amd-display-reduce-number-of-arguments-of-dml31-.patch-21191 +drm-amd-display-mark-dml30-s-useminimumdcfclk-as-noi.patch +drm-rockchip-fix-return-type-of-cdn_dp_connector_mod.patch +gpio-mt7621-make-the-irqchip-immutable.patch