From: Chen-Yu Tsai <wens@csie.org>
Date: Wed, 26 Sep 2018 04:53:57 +0000 (+0800)
Subject: arm64: dts: rockchip: Enable SPI NOR flash on Rock64
X-Git-Tag: v4.20-rc1~66^2~12^2~4
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cd7ab133db383204c9712e1c6fe9dcaa14f90955;p=thirdparty%2Fkernel%2Flinux.git

arm64: dts: rockchip: Enable SPI NOR flash on Rock64

The Pine64 Rock64 board comes with a GigaDevice GD25Q128CSIG
or GD25Q127CSIG chip, which is a 128 Mbit SPI NOR flash chip
that supports the JEDEC read-ID command.

This patch enables the SPI controller and adds a device node
for the flash chip using the generic "jedec,spi-nor" comaptible.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
index 9ee4f57557f3f..2170cf63845ed 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
@@ -290,6 +290,18 @@
 	};
 };
 
+&spi0 {
+	status = "okay";
+
+	spiflash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+
+		/* maximum speed for Rockchip SPI */
+		spi-max-frequency = <50000000>;
+	};
+};
+
 &tsadc {
 	rockchip,hw-tshut-mode = <0>;
 	rockchip,hw-tshut-polarity = <0>;