From: Greg Kroah-Hartman Date: Sat, 23 Aug 2025 11:27:43 +0000 (+0200) Subject: 6.12-stable patches X-Git-Tag: v6.16.3~10 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cdf85f9c39d73e3a84c199d19e13d6d64e520791;p=thirdparty%2Fkernel%2Fstable-queue.git 6.12-stable patches added patches: arm64-dts-ti-k3-am6-add-boot-phase-flag-to-support-mmc-boot.patch arm64-dts-ti-k3-am6-remove-disable-wp-for-emmc.patch arm64-dts-ti-k3-am62-add-non-removable-flag-for-emmc.patch arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch btrfs-subpage-keep-towrite-tag-until-folio-is-cleaned.patch ext4-preserve-sb_i_version-on-remount.patch iio-adc-ad7173-fix-setting-odr-in-probe.patch mark-xe-driver-as-broken-if-kernel-page-size-is-not-4kb.patch mptcp-disable-add_addr-retransmission-when-timeout-is-0.patch mptcp-remove-duplicate-sk_reset_timer-call.patch pci-imx6-add-i.mx8q-pcie-endpoint-ep-support.patch pci-imx6-add-imx8mq_ep-third-64-bit-bar-in-epc_features.patch pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch pci-rockchip-use-standard-pcie-definitions.patch scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch --- diff --git a/queue-6.12/arm64-dts-ti-k3-am6-add-boot-phase-flag-to-support-mmc-boot.patch b/queue-6.12/arm64-dts-ti-k3-am6-add-boot-phase-flag-to-support-mmc-boot.patch new file mode 100644 index 0000000000..9fd7a4b7be --- /dev/null +++ b/queue-6.12/arm64-dts-ti-k3-am6-add-boot-phase-flag-to-support-mmc-boot.patch @@ -0,0 +1,99 @@ +From stable+bounces-172419-greg=kroah.com@vger.kernel.org Fri Aug 22 16:20:03 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:16:12 -0400 +Subject: arm64: dts: ti: k3-am6*: Add boot phase flag to support MMC boot +To: stable@vger.kernel.org +Cc: Judith Mendez , Moteen Shah , Nishanth Menon , Sasha Levin +Message-ID: <20250822141615.1255693-1-sashal@kernel.org> + +From: Judith Mendez + +[ Upstream commit db3cd905b8c8cd40f15a34e30a225704bb8a2fcb ] + +The bootph-all flag was introduced in dt-schema +(dtschema/schemas/bootph.yaml) to define node usage across +different boot phases. + +For eMMC and SD boot modes, voltage regulator nodes, io-expander +nodes, gpio nodes, and MMC nodes need to be present in all boot +stages, so add missing bootph-all phase flag to these nodes to +support SD boot and eMMC boot. + +Signed-off-by: Judith Mendez +Reviewed-by: Moteen Shah +Link: https://lore.kernel.org/r/20250429151454.4160506-2-jm@ti.com +Signed-off-by: Nishanth Menon +Stable-dep-of: a0b8da04153e ("arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 12 ++++++++++++ + arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ + 2 files changed, 14 insertions(+) + +--- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +@@ -69,6 +69,7 @@ + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; ++ bootph-all; + }; + }; + +@@ -77,12 +78,14 @@ + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ + >; ++ bootph-all; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ + >; ++ bootph-all; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { +@@ -118,6 +121,7 @@ + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; ++ bootph-all; + }; + + exp2: gpio@23 { +@@ -229,6 +233,14 @@ + DVDD-supply = <&buck2_reg>; + }; + ++&main_gpio0 { ++ bootph-all; ++}; ++ ++&main_gpio1 { ++ bootph-all; ++}; ++ + &gpmc0 { + ranges = <0 0 0x00 0x51000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + }; +--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +@@ -301,6 +301,7 @@ + AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ + AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ + >; ++ bootph-all; + }; + + main_mmc1_pins_default: main-mmc1-default-pins { +@@ -603,6 +604,7 @@ + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; ++ bootph-all; + }; + + &sdhci1 { diff --git a/queue-6.12/arm64-dts-ti-k3-am6-remove-disable-wp-for-emmc.patch b/queue-6.12/arm64-dts-ti-k3-am6-remove-disable-wp-for-emmc.patch new file mode 100644 index 0000000000..c8ec460530 --- /dev/null +++ b/queue-6.12/arm64-dts-ti-k3-am6-remove-disable-wp-for-emmc.patch @@ -0,0 +1,137 @@ +From stable+bounces-172421-greg=kroah.com@vger.kernel.org Fri Aug 22 16:21:53 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:16:14 -0400 +Subject: arm64: dts: ti: k3-am6*: Remove disable-wp for eMMC +To: stable@vger.kernel.org +Cc: Judith Mendez , Moteen Shah , Nishanth Menon , Sasha Levin +Message-ID: <20250822141615.1255693-3-sashal@kernel.org> + +From: Judith Mendez + +[ Upstream commit ef839ba8142f14513ba396a033110526b7008096 ] + +Remove disable-wp flag for eMMC nodes since this flag is +only applicable to SD according to the binding doc +(mmc/mmc-controller-common.yaml). + +For eMMC, this flag should be ignored but lets remove +anyways to cleanup sdhci nodes. + +Signed-off-by: Judith Mendez +Reviewed-by: Moteen Shah +Link: https://lore.kernel.org/r/20250429151454.4160506-4-jm@ti.com +Signed-off-by: Nishanth Menon +Stable-dep-of: a0b8da04153e ("arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 - + arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 - + arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 1 - + arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 1 - + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 - + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 - + arch/arm64/boot/dts/ti/k3-am642-evm.dts | 1 - + arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 - + arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi | 1 - + arch/arm64/boot/dts/ti/k3-am69-sk.dts | 1 - + 10 files changed, 10 deletions(-) + +--- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +@@ -317,7 +317,6 @@ + &sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; +- disable-wp; + non-removable; + status = "okay"; + }; +--- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts ++++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +@@ -821,7 +821,6 @@ + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_default>; +- disable-wp; + status = "okay"; + }; + +--- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +@@ -324,7 +324,6 @@ + &sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; +- disable-wp; + non-removable; + status = "okay"; + }; +--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +@@ -603,7 +603,6 @@ + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; +- disable-wp; + bootph-all; + }; + +--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +@@ -446,7 +446,6 @@ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; +- disable-wp; + bootph-all; + }; + +--- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +@@ -419,7 +419,6 @@ + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; +- disable-wp; + }; + + &sdhci1 { +--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts ++++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts +@@ -584,7 +584,6 @@ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; +- disable-wp; + bootph-all; + }; + +--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts ++++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +@@ -456,7 +456,6 @@ + bus-width = <8>; + non-removable; + ti,driver-strength-ohm = <50>; +- disable-wp; + }; + + /* +--- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi +@@ -50,5 +50,4 @@ + bus-width = <8>; + non-removable; + ti,driver-strength-ohm = <50>; +- disable-wp; + }; +--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts +@@ -926,7 +926,6 @@ + status = "okay"; + non-removable; + ti,driver-strength-ohm = <50>; +- disable-wp; + }; + + &main_sdhci1 { diff --git a/queue-6.12/arm64-dts-ti-k3-am62-add-non-removable-flag-for-emmc.patch b/queue-6.12/arm64-dts-ti-k3-am62-add-non-removable-flag-for-emmc.patch new file mode 100644 index 0000000000..37285c0039 --- /dev/null +++ b/queue-6.12/arm64-dts-ti-k3-am62-add-non-removable-flag-for-emmc.patch @@ -0,0 +1,59 @@ +From stable+bounces-172420-greg=kroah.com@vger.kernel.org Fri Aug 22 16:19:56 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:16:13 -0400 +Subject: arm64: dts: ti: k3-am62*: Add non-removable flag for eMMC +To: stable@vger.kernel.org +Cc: Judith Mendez , Udit Kumar , Nishanth Menon , Sasha Levin +Message-ID: <20250822141615.1255693-2-sashal@kernel.org> + +From: Judith Mendez + +[ Upstream commit d16e7d34352c4107a81888e9aab4ea4748076e70 ] + +EMMC device is non-removable so add 'non-removable' DT +property to avoid having to redetect the eMMC after +suspend/resume. + +Signed-off-by: Judith Mendez +Reviewed-by: Udit Kumar +Link: https://lore.kernel.org/r/20250429151454.4160506-3-jm@ti.com +Signed-off-by: Nishanth Menon +Stable-dep-of: a0b8da04153e ("arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 + + arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 1 + + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 + + 3 files changed, 3 insertions(+) + +--- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts ++++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +@@ -818,6 +818,7 @@ + + &sdhci0 { + bootph-all; ++ non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins_default>; + disable-wp; +--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +@@ -444,6 +444,7 @@ + + &sdhci0 { + status = "okay"; ++ non-removable; + ti,driver-strength-ohm = <50>; + disable-wp; + bootph-all; +--- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +@@ -416,6 +416,7 @@ + &sdhci0 { + bootph-all; + status = "okay"; ++ non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + disable-wp; diff --git a/queue-6.12/arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch b/queue-6.12/arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch new file mode 100644 index 0000000000..8992628724 --- /dev/null +++ b/queue-6.12/arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch @@ -0,0 +1,153 @@ +From stable+bounces-172422-greg=kroah.com@vger.kernel.org Fri Aug 22 16:20:54 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:16:15 -0400 +Subject: arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board file +To: stable@vger.kernel.org +Cc: Judith Mendez , Vignesh Raghavendra , Sasha Levin +Message-ID: <20250822141615.1255693-4-sashal@kernel.org> + +From: Judith Mendez + +[ Upstream commit a0b8da04153eb61cc2eaeeea5cc404e91e557f6b ] + +This moves pinmux child nodes for sdhci0 node from k3-am62x-sk-common +to each top level board file. This is needed since we require internal +pullups for AM62x SK and not for AM62 LP SK since it has external +pullups on DATA 1-7. + +Internal pulls are required for AM62 SK as per JESD84 spec +recommendation to prevent unconnected lines floating. + +Fixes: d19a66ae488a ("arm64: dts: ti: k3-am625-sk: Enable on board peripherals") +Cc: stable@vger.kernel.org +Signed-off-by: Judith Mendez +Link: https://lore.kernel.org/r/20250707190830.3951619-1-jm@ti.com +Signed-off-by: Vignesh Raghavendra +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 24 ++++++++++++++++++++++++ + arch/arm64/boot/dts/ti/k3-am625-sk.dts | 24 ++++++++++++++++++++++++ + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 24 ------------------------ + 3 files changed, 48 insertions(+), 24 deletions(-) + +--- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +@@ -74,6 +74,22 @@ + }; + + &main_pmx0 { ++ main_mmc0_pins_default: main-mmc0-default-pins { ++ bootph-all; ++ pinctrl-single,pins = < ++ AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (V3) MMC0_CMD */ ++ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (Y1) MMC0_CLK */ ++ AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (V2) MMC0_DAT0 */ ++ AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (V1) MMC0_DAT1 */ ++ AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (W2) MMC0_DAT2 */ ++ AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (W1) MMC0_DAT3 */ ++ AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (Y2) MMC0_DAT4 */ ++ AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (W3) MMC0_DAT5 */ ++ AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (W4) MMC0_DAT6 */ ++ AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (V4) MMC0_DAT7 */ ++ >; ++ }; ++ + vddshv_sdio_pins_default: vddshv-sdio-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ +@@ -144,6 +160,14 @@ + }; + }; + ++&sdhci0 { ++ bootph-all; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_mmc0_pins_default>; ++ status = "okay"; ++}; ++ + &sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vddshv_sdio>; +--- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts ++++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts +@@ -106,6 +106,22 @@ + }; + + &main_pmx0 { ++ main_mmc0_pins_default: main-mmc0-default-pins { ++ bootph-all; ++ pinctrl-single,pins = < ++ AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ ++ AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ ++ AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ ++ AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ ++ AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ ++ AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ ++ AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ ++ AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ ++ AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ ++ AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ ++ >; ++ }; ++ + main_rgmii2_pins_default: main-rgmii2-default-pins { + bootph-all; + pinctrl-single,pins = < +@@ -195,6 +211,14 @@ + }; + }; + ++&sdhci0 { ++ bootph-all; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&main_mmc0_pins_default>; ++ status = "okay"; ++}; ++ + &sdhci1 { + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; +--- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi ++++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +@@ -182,22 +182,6 @@ + >; + }; + +- main_mmc0_pins_default: main-mmc0-default-pins { +- bootph-all; +- pinctrl-single,pins = < +- AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ +- AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ +- AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */ +- AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */ +- AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */ +- AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */ +- AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */ +- AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */ +- AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */ +- AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ +- >; +- }; +- + main_mmc1_pins_default: main-mmc1-default-pins { + bootph-all; + pinctrl-single,pins = < +@@ -413,14 +397,6 @@ + clock-frequency = <400000>; + }; + +-&sdhci0 { +- bootph-all; +- status = "okay"; +- non-removable; +- pinctrl-names = "default"; +- pinctrl-0 = <&main_mmc0_pins_default>; +-}; +- + &sdhci1 { + /* SD/MMC */ + bootph-all; diff --git a/queue-6.12/btrfs-subpage-keep-towrite-tag-until-folio-is-cleaned.patch b/queue-6.12/btrfs-subpage-keep-towrite-tag-until-folio-is-cleaned.patch new file mode 100644 index 0000000000..7cb9d40e37 --- /dev/null +++ b/queue-6.12/btrfs-subpage-keep-towrite-tag-until-folio-is-cleaned.patch @@ -0,0 +1,130 @@ +From stable+bounces-172402-greg=kroah.com@vger.kernel.org Fri Aug 22 16:09:13 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:01:35 -0400 +Subject: btrfs: subpage: keep TOWRITE tag until folio is cleaned +To: stable@vger.kernel.org +Cc: Naohiro Aota , Qu Wenruo , Johannes Thumshirn , David Sterba , Sasha Levin +Message-ID: <20250822140136.1246384-1-sashal@kernel.org> + +From: Naohiro Aota + +[ Upstream commit b1511360c8ac882b0c52caa263620538e8d73220 ] + +btrfs_subpage_set_writeback() calls folio_start_writeback() the first time +a folio is written back, and it also clears the PAGECACHE_TAG_TOWRITE tag +even if there are still dirty blocks in the folio. This can break ordering +guarantees, such as those required by btrfs_wait_ordered_extents(). + +That ordering breakage leads to a real failure. For example, running +generic/464 on a zoned setup will hit the following ASSERT. This happens +because the broken ordering fails to flush existing dirty pages before the +file size is truncated. + + assertion failed: !list_empty(&ordered->list) :: 0, in fs/btrfs/zoned.c:1899 + ------------[ cut here ]------------ + kernel BUG at fs/btrfs/zoned.c:1899! + Oops: invalid opcode: 0000 [#1] SMP NOPTI + CPU: 2 UID: 0 PID: 1906169 Comm: kworker/u130:2 Kdump: loaded Not tainted 6.16.0-rc6-BTRFS-ZNS+ #554 PREEMPT(voluntary) + Hardware name: Supermicro Super Server/H12SSL-NT, BIOS 2.0 02/22/2021 + Workqueue: btrfs-endio-write btrfs_work_helper [btrfs] + RIP: 0010:btrfs_finish_ordered_zoned.cold+0x50/0x52 [btrfs] + RSP: 0018:ffffc9002efdbd60 EFLAGS: 00010246 + RAX: 000000000000004c RBX: ffff88811923c4e0 RCX: 0000000000000000 + RDX: 0000000000000000 RSI: ffffffff827e38b1 RDI: 00000000ffffffff + RBP: ffff88810005d000 R08: 00000000ffffdfff R09: ffffffff831051c8 + R10: ffffffff83055220 R11: 0000000000000000 R12: ffff8881c2458c00 + R13: ffff88811923c540 R14: ffff88811923c5e8 R15: ffff8881c1bd9680 + FS: 0000000000000000(0000) GS:ffff88a04acd0000(0000) knlGS:0000000000000000 + CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 + CR2: 00007f907c7a918c CR3: 0000000004024000 CR4: 0000000000350ef0 + Call Trace: + + ? srso_return_thunk+0x5/0x5f + btrfs_finish_ordered_io+0x4a/0x60 [btrfs] + btrfs_work_helper+0xf9/0x490 [btrfs] + process_one_work+0x204/0x590 + ? srso_return_thunk+0x5/0x5f + worker_thread+0x1d6/0x3d0 + ? __pfx_worker_thread+0x10/0x10 + kthread+0x118/0x230 + ? __pfx_kthread+0x10/0x10 + ret_from_fork+0x205/0x260 + ? __pfx_kthread+0x10/0x10 + ret_from_fork_asm+0x1a/0x30 + + +Consider process A calling writepages() with WB_SYNC_NONE. In zoned mode or +for compressed writes, it locks several folios for delalloc and starts +writing them out. Let's call the last locked folio folio X. Suppose the +write range only partially covers folio X, leaving some pages dirty. +Process A calls btrfs_subpage_set_writeback() when building a bio. This +function call clears the TOWRITE tag of folio X, whose size = 8K and +the block size = 4K. It is following state. + + 0 4K 8K + |/////|/////| (flag: DIRTY, tag: DIRTY) + <-----> Process A will write this range. + +Now suppose process B concurrently calls writepages() with WB_SYNC_ALL. It +calls tag_pages_for_writeback() to tag dirty folios with +PAGECACHE_TAG_TOWRITE. Since folio X is still dirty, it gets tagged. Then, +B collects tagged folios using filemap_get_folios_tag() and must wait for +folio X to be written before returning from writepages(). + + 0 4K 8K + |/////|/////| (flag: DIRTY, tag: DIRTY|TOWRITE) + +However, between tagging and collecting, process A may call +btrfs_subpage_set_writeback() and clear folio X's TOWRITE tag. + 0 4K 8K + | |/////| (flag: DIRTY|WRITEBACK, tag: DIRTY) + +As a result, process B won't see folio X in its batch, and returns without +waiting for it. This breaks the WB_SYNC_ALL ordering requirement. + +Fix this by using btrfs_subpage_set_writeback_keepwrite(), which retains +the TOWRITE tag. We now manually clear the tag only after the folio becomes +clean, via the xas operation. + +Fixes: 3470da3b7d87 ("btrfs: subpage: introduce helpers for writeback status") +CC: stable@vger.kernel.org # 6.12+ +Reviewed-by: Qu Wenruo +Reviewed-by: Johannes Thumshirn +Signed-off-by: Naohiro Aota +Signed-off-by: David Sterba +[ Adjust context ] +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + fs/btrfs/subpage.c | 19 ++++++++++++++++++- + 1 file changed, 18 insertions(+), 1 deletion(-) + +--- a/fs/btrfs/subpage.c ++++ b/fs/btrfs/subpage.c +@@ -452,8 +452,25 @@ void btrfs_subpage_set_writeback(const s + + spin_lock_irqsave(&subpage->lock, flags); + bitmap_set(subpage->bitmaps, start_bit, len >> fs_info->sectorsize_bits); ++ ++ /* ++ * Don't clear the TOWRITE tag when starting writeback on a still-dirty ++ * folio. Doing so can cause WB_SYNC_ALL writepages() to overlook it, ++ * assume writeback is complete, and exit too early — violating sync ++ * ordering guarantees. ++ */ + if (!folio_test_writeback(folio)) +- folio_start_writeback(folio); ++ __folio_start_writeback(folio, true); ++ if (!folio_test_dirty(folio)) { ++ struct address_space *mapping = folio_mapping(folio); ++ XA_STATE(xas, &mapping->i_pages, folio->index); ++ unsigned long flags; ++ ++ xas_lock_irqsave(&xas, flags); ++ xas_load(&xas); ++ xas_clear_mark(&xas, PAGECACHE_TAG_TOWRITE); ++ xas_unlock_irqrestore(&xas, flags); ++ } + spin_unlock_irqrestore(&subpage->lock, flags); + } + diff --git a/queue-6.12/ext4-preserve-sb_i_version-on-remount.patch b/queue-6.12/ext4-preserve-sb_i_version-on-remount.patch new file mode 100644 index 0000000000..0fbcf225d3 --- /dev/null +++ b/queue-6.12/ext4-preserve-sb_i_version-on-remount.patch @@ -0,0 +1,60 @@ +From stable+bounces-172414-greg=kroah.com@vger.kernel.org Fri Aug 22 16:15:38 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:11:26 -0400 +Subject: ext4: preserve SB_I_VERSION on remount +To: stable@vger.kernel.org +Cc: Baokun Li , stable@kernel.org, Jan Kara , Theodore Ts'o , Sasha Levin +Message-ID: <20250822141126.1253416-1-sashal@kernel.org> + +From: Baokun Li + +[ Upstream commit f2326fd14a224e4cccbab89e14c52279ff79b7ec ] + +IMA testing revealed that after an ext4 remount, file accesses triggered +full measurements even without modifications, instead of skipping as +expected when i_version is unchanged. + +Debugging showed `SB_I_VERSION` was cleared in reconfigure_super() during +remount due to commit 1ff20307393e ("ext4: unconditionally enable the +i_version counter") removing the fix from commit 960e0ab63b2e ("ext4: fix +i_version handling on remount"). + +To rectify this, `SB_I_VERSION` is always set for `fc->sb_flags` in +ext4_init_fs_context(), instead of `sb->s_flags` in __ext4_fill_super(), +ensuring it persists across all mounts. + +Cc: stable@kernel.org +Fixes: 1ff20307393e ("ext4: unconditionally enable the i_version counter") +Signed-off-by: Baokun Li +Reviewed-by: Jan Kara +Link: https://patch.msgid.link/20250703073903.6952-2-libaokun@huaweicloud.com +Signed-off-by: Theodore Ts'o +[ Adjust context ] +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + fs/ext4/super.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/fs/ext4/super.c ++++ b/fs/ext4/super.c +@@ -2019,6 +2019,9 @@ int ext4_init_fs_context(struct fs_conte + fc->fs_private = ctx; + fc->ops = &ext4_context_ops; + ++ /* i_version is always enabled now */ ++ fc->sb_flags |= SB_I_VERSION; ++ + return 0; + } + +@@ -5277,9 +5280,6 @@ static int __ext4_fill_super(struct fs_c + sb->s_flags = (sb->s_flags & ~SB_POSIXACL) | + (test_opt(sb, POSIX_ACL) ? SB_POSIXACL : 0); + +- /* i_version is always enabled now */ +- sb->s_flags |= SB_I_VERSION; +- + err = ext4_check_feature_compatibility(sb, es, silent); + if (err) + goto failed_mount; diff --git a/queue-6.12/iio-adc-ad7173-fix-setting-odr-in-probe.patch b/queue-6.12/iio-adc-ad7173-fix-setting-odr-in-probe.patch new file mode 100644 index 0000000000..2dd39868e0 --- /dev/null +++ b/queue-6.12/iio-adc-ad7173-fix-setting-odr-in-probe.patch @@ -0,0 +1,52 @@ +From stable+bounces-172487-greg=kroah.com@vger.kernel.org Fri Aug 22 20:10:18 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 14:08:10 -0400 +Subject: iio: adc: ad7173: fix setting ODR in probe +To: stable@vger.kernel.org +Cc: David Lechner , Stable@vger.kernel.org, Jonathan Cameron , Sasha Levin +Message-ID: <20250822180810.1356484-1-sashal@kernel.org> + +From: David Lechner + +[ Upstream commit 6fa908abd19cc35c205f343b79c67ff38dbc9b76 ] + +Fix the setting of the ODR register value in the probe function for +AD7177. The AD7177 chip has a different ODR value after reset than the +other chips (0x7 vs. 0x0) and 0 is a reserved value on that chip. + +The driver already has this information available in odr_start_value +and uses it when checking valid values when writing to the +sampling_frequency attribute, but failed to set the correct initial +value in the probe function. + +Fixes: 37ae8381ccda ("iio: adc: ad7173: add support for additional models") +Signed-off-by: David Lechner +Link: https://patch.msgid.link/20250710-iio-adc-ad7173-fix-setting-odr-in-probe-v1-1-78a100fec998@baylibre.com +Cc: +Signed-off-by: Jonathan Cameron +[ Adjust context ] +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/iio/adc/ad7173.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/iio/adc/ad7173.c ++++ b/drivers/iio/adc/ad7173.c +@@ -1243,6 +1243,7 @@ static int ad7173_fw_parse_channel_confi + chan_st_priv->cfg.bipolar = false; + chan_st_priv->cfg.input_buf = st->info->has_input_buf; + chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF; ++ chan_st_priv->cfg.odr = st->info->odr_start_value; + st->adc_mode |= AD7173_ADC_MODE_REF_EN; + + chan_index++; +@@ -1307,7 +1308,7 @@ static int ad7173_fw_parse_channel_confi + chan->channel = ain[0]; + chan_st_priv->chan_reg = chan_index; + chan_st_priv->cfg.input_buf = st->info->has_input_buf; +- chan_st_priv->cfg.odr = 0; ++ chan_st_priv->cfg.odr = st->info->odr_start_value; + + chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar"); + if (chan_st_priv->cfg.bipolar) diff --git a/queue-6.12/mark-xe-driver-as-broken-if-kernel-page-size-is-not-4kb.patch b/queue-6.12/mark-xe-driver-as-broken-if-kernel-page-size-is-not-4kb.patch new file mode 100644 index 0000000000..c09939f611 --- /dev/null +++ b/queue-6.12/mark-xe-driver-as-broken-if-kernel-page-size-is-not-4kb.patch @@ -0,0 +1,41 @@ +From stable+bounces-172516-greg=kroah.com@vger.kernel.org Fri Aug 22 22:31:46 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 16:30:36 -0400 +Subject: Mark xe driver as BROKEN if kernel page size is not 4kB +To: stable@vger.kernel.org +Cc: "Simon Richter" , "Thomas Hellström" , "Rodrigo Vivi" , "Sasha Levin" +Message-ID: <20250822203036.1485683-1-sashal@kernel.org> + +From: Simon Richter + +[ Upstream commit 022906afdf90327bce33d52fb4fb41b6c7d618fb ] + +This driver, for the time being, assumes that the kernel page size is 4kB, +so it fails on loong64 and aarch64 with 16kB pages, and ppc64el with 64kB +pages. + +Signed-off-by: Simon Richter +Reviewed-by: Thomas Hellström +Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") +Cc: stable@vger.kernel.org # v6.8+ +Signed-off-by: Thomas Hellström +Link: https://lore.kernel.org/r/20250802024152.3021-1-Simon.Richter@hogyros.de +(cherry picked from commit 0521a868222ffe636bf202b6e9d29292c1e19c62) +Signed-off-by: Rodrigo Vivi +[ Adjust context ] +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/xe/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/xe/Kconfig ++++ b/drivers/gpu/drm/xe/Kconfig +@@ -3,6 +3,7 @@ config DRM_XE + tristate "Intel Xe Graphics" + depends on DRM && PCI && MMU + depends on KUNIT || !KUNIT ++ depends on PAGE_SIZE_4KB || COMPILE_TEST || BROKEN + select INTERVAL_TREE + # we need shmfs for the swappable backing store, and in particular + # the shmem_readpage() which depends upon tmpfs diff --git a/queue-6.12/mptcp-disable-add_addr-retransmission-when-timeout-is-0.patch b/queue-6.12/mptcp-disable-add_addr-retransmission-when-timeout-is-0.patch new file mode 100644 index 0000000000..c3f094e3e1 --- /dev/null +++ b/queue-6.12/mptcp-disable-add_addr-retransmission-when-timeout-is-0.patch @@ -0,0 +1,95 @@ +From f5ce0714623cffd00bf2a83e890d09c609b7f50a Mon Sep 17 00:00:00 2001 +From: Geliang Tang +Date: Fri, 15 Aug 2025 19:28:23 +0200 +Subject: mptcp: disable add_addr retransmission when timeout is 0 + +From: Geliang Tang + +commit f5ce0714623cffd00bf2a83e890d09c609b7f50a upstream. + +When add_addr_timeout was set to 0, this caused the ADD_ADDR to be +retransmitted immediately, which looks like a buggy behaviour. Instead, +interpret 0 as "no retransmissions needed". + +The documentation is updated to explicitly state that setting the timeout +to 0 disables retransmission. + +Fixes: 93f323b9cccc ("mptcp: add a new sysctl add_addr_timeout") +Cc: stable@vger.kernel.org +Suggested-by: Matthieu Baerts +Signed-off-by: Geliang Tang +Reviewed-by: Matthieu Baerts (NGI0) +Signed-off-by: Matthieu Baerts (NGI0) +Link: https://patch.msgid.link/20250815-net-mptcp-misc-fixes-6-17-rc2-v1-5-521fe9957892@kernel.org +Signed-off-by: Jakub Kicinski +[ Before commit e4c28e3d5c09 ("mptcp: pm: move generic PM helpers to + pm.c"), mptcp_pm_alloc_anno_list() was in pm_netlink.c. The same patch + can be applied there without conflicts. ] +Signed-off-by: Matthieu Baerts (NGI0) +Signed-off-by: Greg Kroah-Hartman +--- + Documentation/networking/mptcp-sysctl.rst | 2 ++ + net/mptcp/pm_netlink.c | 13 ++++++++++--- + 2 files changed, 12 insertions(+), 3 deletions(-) + +--- a/Documentation/networking/mptcp-sysctl.rst ++++ b/Documentation/networking/mptcp-sysctl.rst +@@ -12,6 +12,8 @@ add_addr_timeout - INTEGER (seconds) + resent to an MPTCP peer that has not acknowledged a previous + ADD_ADDR message. + ++ Do not retransmit if set to 0. ++ + The default value matches TCP_RTO_MAX. This is a per-namespace + sysctl. + +--- a/net/mptcp/pm_netlink.c ++++ b/net/mptcp/pm_netlink.c +@@ -293,6 +293,7 @@ static void mptcp_pm_add_timer(struct ti + struct mptcp_pm_add_entry *entry = from_timer(entry, timer, add_timer); + struct mptcp_sock *msk = entry->sock; + struct sock *sk = (struct sock *)msk; ++ unsigned int timeout; + + pr_debug("msk=%p\n", msk); + +@@ -310,6 +311,10 @@ static void mptcp_pm_add_timer(struct ti + goto out; + } + ++ timeout = mptcp_get_add_addr_timeout(sock_net(sk)); ++ if (!timeout) ++ goto out; ++ + spin_lock_bh(&msk->pm.lock); + + if (!mptcp_pm_should_add_signal_addr(msk)) { +@@ -321,7 +326,7 @@ static void mptcp_pm_add_timer(struct ti + + if (entry->retrans_times < ADD_ADDR_RETRANS_MAX) + sk_reset_timer(sk, timer, +- jiffies + mptcp_get_add_addr_timeout(sock_net(sk))); ++ jiffies + timeout); + + spin_unlock_bh(&msk->pm.lock); + +@@ -363,6 +368,7 @@ bool mptcp_pm_alloc_anno_list(struct mpt + struct mptcp_pm_add_entry *add_entry = NULL; + struct sock *sk = (struct sock *)msk; + struct net *net = sock_net(sk); ++ unsigned int timeout; + + lockdep_assert_held(&msk->pm.lock); + +@@ -387,8 +393,9 @@ bool mptcp_pm_alloc_anno_list(struct mpt + + timer_setup(&add_entry->add_timer, mptcp_pm_add_timer, 0); + reset_timer: +- sk_reset_timer(sk, &add_entry->add_timer, +- jiffies + mptcp_get_add_addr_timeout(net)); ++ timeout = mptcp_get_add_addr_timeout(net); ++ if (timeout) ++ sk_reset_timer(sk, &add_entry->add_timer, jiffies + timeout); + + return true; + } diff --git a/queue-6.12/mptcp-remove-duplicate-sk_reset_timer-call.patch b/queue-6.12/mptcp-remove-duplicate-sk_reset_timer-call.patch new file mode 100644 index 0000000000..58a4dbf84b --- /dev/null +++ b/queue-6.12/mptcp-remove-duplicate-sk_reset_timer-call.patch @@ -0,0 +1,54 @@ +From 5d13349472ac8abcbcb94407969aa0fdc2e1f1be Mon Sep 17 00:00:00 2001 +From: Geliang Tang +Date: Fri, 15 Aug 2025 19:28:22 +0200 +Subject: mptcp: remove duplicate sk_reset_timer call + +From: Geliang Tang + +commit 5d13349472ac8abcbcb94407969aa0fdc2e1f1be upstream. + +sk_reset_timer() was called twice in mptcp_pm_alloc_anno_list. + +Simplify the code by using a 'goto' statement to eliminate the +duplication. + +Note that this is not a fix, but it will help backporting the following +patch. The same "Fixes" tag has been added for this reason. + +Fixes: 93f323b9cccc ("mptcp: add a new sysctl add_addr_timeout") +Cc: stable@vger.kernel.org +Signed-off-by: Geliang Tang +Reviewed-by: Matthieu Baerts (NGI0) +Signed-off-by: Matthieu Baerts (NGI0) +Link: https://patch.msgid.link/20250815-net-mptcp-misc-fixes-6-17-rc2-v1-4-521fe9957892@kernel.org +Signed-off-by: Jakub Kicinski +[ Before commit e4c28e3d5c09 ("mptcp: pm: move generic PM helpers to + pm.c"), mptcp_pm_alloc_anno_list() was in pm_netlink.c. The same patch + can be applied there without conflicts. ] +Signed-off-by: Matthieu Baerts (NGI0) +Signed-off-by: Greg Kroah-Hartman +--- + net/mptcp/pm_netlink.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +--- a/net/mptcp/pm_netlink.c ++++ b/net/mptcp/pm_netlink.c +@@ -372,9 +372,7 @@ bool mptcp_pm_alloc_anno_list(struct mpt + if (WARN_ON_ONCE(mptcp_pm_is_kernel(msk))) + return false; + +- sk_reset_timer(sk, &add_entry->add_timer, +- jiffies + mptcp_get_add_addr_timeout(net)); +- return true; ++ goto reset_timer; + } + + add_entry = kmalloc(sizeof(*add_entry), GFP_ATOMIC); +@@ -388,6 +386,7 @@ bool mptcp_pm_alloc_anno_list(struct mpt + add_entry->retrans_times = 0; + + timer_setup(&add_entry->add_timer, mptcp_pm_add_timer, 0); ++reset_timer: + sk_reset_timer(sk, &add_entry->add_timer, + jiffies + mptcp_get_add_addr_timeout(net)); + diff --git a/queue-6.12/pci-imx6-add-i.mx8q-pcie-endpoint-ep-support.patch b/queue-6.12/pci-imx6-add-i.mx8q-pcie-endpoint-ep-support.patch new file mode 100644 index 0000000000..5963dd71a6 --- /dev/null +++ b/queue-6.12/pci-imx6-add-i.mx8q-pcie-endpoint-ep-support.patch @@ -0,0 +1,81 @@ +From stable+bounces-172505-greg=kroah.com@vger.kernel.org Fri Aug 22 21:18:15 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 15:17:49 -0400 +Subject: PCI: imx6: Add i.MX8Q PCIe Endpoint (EP) support +To: stable@vger.kernel.org +Cc: "Frank Li" , "Krzysztof Wilczyński" , "Bjorn Helgaas" , "Richard Zhu" , "Manivannan Sadhasivam" , "Sasha Levin" +Message-ID: <20250822191750.1437890-1-sashal@kernel.org> + +From: Frank Li + +[ Upstream commit 687aedb73a401addf151c5f60e481e574b4c9ad9 ] + +Add support for the i.MX8Q series (i.MX8QM, i.MX8QXP, and i.MX8DXL) PCIe +Endpoint (EP). On the i.MX8Q platforms, the PCI bus addresses differ +from the CPU addresses. However, the DesignWare (DWC) driver already +handles this in the common code. + +Link: https://lore.kernel.org/r/20241119-pci_fixup_addr-v8-7-c4bfa5193288@nxp.com +Signed-off-by: Frank Li +[kwilczynski: commit log] +Signed-off-by: Krzysztof Wilczyński +Signed-off-by: Bjorn Helgaas +Reviewed-by: Richard Zhu +Reviewed-by: Manivannan Sadhasivam +Stable-dep-of: c523fa63ac1d ("PCI: imx6: Add IMX8MQ_EP third 64-bit BAR in epc_features") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/dwc/pci-imx6.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -72,6 +72,7 @@ enum imx_pcie_variants { + IMX8MQ_EP, + IMX8MM_EP, + IMX8MP_EP, ++ IMX8Q_EP, + IMX95_EP, + }; + +@@ -1103,6 +1104,16 @@ static const struct pci_epc_features imx + .align = SZ_64K, + }; + ++static const struct pci_epc_features imx8q_pcie_epc_features = { ++ .linkup_notifier = false, ++ .msi_capable = true, ++ .msix_capable = false, ++ .bar[BAR_1] = { .type = BAR_RESERVED, }, ++ .bar[BAR_3] = { .type = BAR_RESERVED, }, ++ .bar[BAR_5] = { .type = BAR_RESERVED, }, ++ .align = SZ_64K, ++}; ++ + /* + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme + * ================================================================================================ +@@ -1695,6 +1706,14 @@ static const struct imx_pcie_drvdata drv + .epc_features = &imx8m_pcie_epc_features, + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, + }, ++ [IMX8Q_EP] = { ++ .variant = IMX8Q_EP, ++ .flags = IMX_PCIE_FLAG_HAS_PHYDRV, ++ .mode = DW_PCIE_EP_TYPE, ++ .epc_features = &imx8q_pcie_epc_features, ++ .clk_names = imx8q_clks, ++ .clks_cnt = ARRAY_SIZE(imx8q_clks), ++ }, + [IMX95_EP] = { + .variant = IMX95_EP, + .flags = IMX_PCIE_FLAG_HAS_SERDES | +@@ -1724,6 +1743,7 @@ static const struct of_device_id imx_pci + { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, + { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, + { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, ++ { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], }, + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, + {}, + }; diff --git a/queue-6.12/pci-imx6-add-imx8mq_ep-third-64-bit-bar-in-epc_features.patch b/queue-6.12/pci-imx6-add-imx8mq_ep-third-64-bit-bar-in-epc_features.patch new file mode 100644 index 0000000000..7545380344 --- /dev/null +++ b/queue-6.12/pci-imx6-add-imx8mq_ep-third-64-bit-bar-in-epc_features.patch @@ -0,0 +1,40 @@ +From stable+bounces-172506-greg=kroah.com@vger.kernel.org Fri Aug 22 21:20:18 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 15:17:50 -0400 +Subject: PCI: imx6: Add IMX8MQ_EP third 64-bit BAR in epc_features +To: stable@vger.kernel.org +Cc: Richard Zhu , Bjorn Helgaas , Frank Li , Sasha Levin +Message-ID: <20250822191750.1437890-2-sashal@kernel.org> + +From: Richard Zhu + +[ Upstream commit c523fa63ac1d452abeeb4e699560ec3365037f32 ] + +IMX8MQ_EP has three 64-bit BAR0/2/4 capable and programmable BARs. For +IMX8MQ_EP, use imx8q_pcie_epc_features (64-bit BARs 0, 2, 4) instead +of imx8m_pcie_epc_features (64-bit BARs 0, 2). + +Fixes: 75c2f26da03f ("PCI: imx6: Add i.MX PCIe EP mode support") +Signed-off-by: Richard Zhu +[bhelgaas: add details in subject] +Signed-off-by: Bjorn Helgaas +Reviewed-by: Frank Li +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/20250708091003.2582846-2-hongxing.zhu@nxp.com +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/dwc/pci-imx6.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/controller/dwc/pci-imx6.c ++++ b/drivers/pci/controller/dwc/pci-imx6.c +@@ -1676,7 +1676,7 @@ static const struct imx_pcie_drvdata drv + .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, + .mode_off[1] = IOMUXC_GPR12, + .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, +- .epc_features = &imx8m_pcie_epc_features, ++ .epc_features = &imx8q_pcie_epc_features, + .init_phy = imx8mq_pcie_init_phy, + .enable_ref_clk = imx8mm_pcie_enable_ref_clk, + }, diff --git a/queue-6.12/pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch b/queue-6.12/pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch new file mode 100644 index 0000000000..d096da56fa --- /dev/null +++ b/queue-6.12/pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch @@ -0,0 +1,44 @@ +From stable+bounces-172515-greg=kroah.com@vger.kernel.org Fri Aug 22 22:30:09 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 16:29:59 -0400 +Subject: PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining +To: stable@vger.kernel.org +Cc: Geraldo Nascimento , Manivannan Sadhasivam , Bjorn Helgaas , Robin Murphy , Sasha Levin +Message-ID: <20250822202959.1484986-2-sashal@kernel.org> + +From: Geraldo Nascimento + +[ Upstream commit 114b06ee108cabc82b995fbac6672230a9776936 ] + +Rockchip controllers can support up to 5.0 GT/s link speed. But the driver +doesn't set the Target Link Speed currently. This may cause failure in +retraining the link to 5.0 GT/s if supported by the endpoint. So set the +Target Link Speed to 5.0 GT/s in the Link Control and Status Register 2. + +Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") +Signed-off-by: Geraldo Nascimento +[mani: fixed whitespace warning, commit message rewording, added fixes tag] +Signed-off-by: Manivannan Sadhasivam +Signed-off-by: Bjorn Helgaas +Tested-by: Robin Murphy +Cc: stable@vger.kernel.org +Link: https://patch.msgid.link/0afa6bc47b7f50e2e81b0b47d51c66feb0fb565f.1751322015.git.geraldogabriel@gmail.com +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/pci/controller/pcie-rockchip-host.c ++++ b/drivers/pci/controller/pcie-rockchip-host.c +@@ -342,6 +342,10 @@ static int rockchip_pcie_host_init_port( + * Enable retrain for gen2. This should be configured only after + * gen1 finished. + */ ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); ++ status &= ~PCI_EXP_LNKCTL2_TLS; ++ status |= PCI_EXP_LNKCTL2_TLS_5_0GT; ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKCTL_RL; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); diff --git a/queue-6.12/pci-rockchip-use-standard-pcie-definitions.patch b/queue-6.12/pci-rockchip-use-standard-pcie-definitions.patch new file mode 100644 index 0000000000..69efab9e26 --- /dev/null +++ b/queue-6.12/pci-rockchip-use-standard-pcie-definitions.patch @@ -0,0 +1,162 @@ +From stable+bounces-172514-greg=kroah.com@vger.kernel.org Fri Aug 22 22:32:24 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 16:29:58 -0400 +Subject: PCI: rockchip: Use standard PCIe definitions +To: stable@vger.kernel.org +Cc: Geraldo Nascimento , Bjorn Helgaas , Manivannan Sadhasivam , Sasha Levin +Message-ID: <20250822202959.1484986-1-sashal@kernel.org> + +From: Geraldo Nascimento + +[ Upstream commit cbbfe9f683f0f9b6a1da2eaa53b995a4b5961086 ] + +Current code uses custom-defined register offsets and bitfields for the +standard PCIe registers. This creates duplication as the PCI header already +defines them. So, switch to using the standard PCIe definitions and drop +the custom ones. + +Suggested-by: Bjorn Helgaas +Signed-off-by: Geraldo Nascimento +[mani: commit message rewording] +Signed-off-by: Manivannan Sadhasivam +[bhelgaas: include bitfield.h] +Signed-off-by: Bjorn Helgaas +Link: https://patch.msgid.link/e81700ef4b49f584bc8834bfb07b6d8995fc1f42.1751322015.git.geraldogabriel@gmail.com +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/pci/controller/pcie-rockchip-host.c | 45 ++++++++++++++-------------- + drivers/pci/controller/pcie-rockchip.h | 11 ------ + 2 files changed, 24 insertions(+), 32 deletions(-) + +--- a/drivers/pci/controller/pcie-rockchip-host.c ++++ b/drivers/pci/controller/pcie-rockchip-host.c +@@ -11,6 +11,7 @@ + * ARM PCI Host generic driver. + */ + ++#include + #include + #include + #include +@@ -40,18 +41,18 @@ static void rockchip_pcie_enable_bw_int( + { + u32 status; + +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE); +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + } + + static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip) + { + u32 status; + +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + } + + static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip) +@@ -269,7 +270,7 @@ static void rockchip_pcie_set_power_limi + scale = 3; /* 0.001x */ + curr = curr / 1000; /* convert to mA */ + power = (curr * 3300) / 1000; /* milliwatt */ +- while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) { ++ while (power > FIELD_MAX(PCI_EXP_DEVCAP_PWR_VAL)) { + if (!scale) { + dev_warn(rockchip->dev, "invalid power supply\n"); + return; +@@ -278,10 +279,10 @@ static void rockchip_pcie_set_power_limi + power = power / 10; + } + +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR); +- status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) | +- (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT); +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); ++ status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_VAL, power); ++ status |= FIELD_PREP(PCI_EXP_DEVCAP_PWR_SCL, scale); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCAP); + } + + /** +@@ -309,14 +310,14 @@ static int rockchip_pcie_host_init_port( + rockchip_pcie_set_power_limit(rockchip); + + /* Set RC's clock architecture as common clock */ +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKSTA_SLC << 16; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + + /* Set RC's RCB to 128 */ +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKCTL_RCB; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + + /* Enable Gen1 training */ + rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE, +@@ -341,9 +342,9 @@ static int rockchip_pcie_host_init_port( + * Enable retrain for gen2. This should be configured only after + * gen1 finished. + */ +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + status |= PCI_EXP_LNKCTL_RL; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); + + err = readl_poll_timeout(rockchip->apb_base + PCIE_CORE_CTRL, + status, PCIE_LINK_IS_GEN2(status), 20, +@@ -380,15 +381,15 @@ static int rockchip_pcie_host_init_port( + + /* Clear L0s from RC's link cap */ + if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP); +- status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP); ++ status &= ~PCI_EXP_LNKCAP_ASPM_L0S; ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCAP); + } + +- status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCSR); +- status &= ~PCIE_RC_CONFIG_DCSR_MPS_MASK; +- status |= PCIE_RC_CONFIG_DCSR_MPS_256; +- rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCSR); ++ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL); ++ status &= ~PCI_EXP_DEVCTL_PAYLOAD; ++ status |= PCI_EXP_DEVCTL_PAYLOAD_256B; ++ rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_DEVCTL); + + return 0; + err_power_off_phy: +--- a/drivers/pci/controller/pcie-rockchip.h ++++ b/drivers/pci/controller/pcie-rockchip.h +@@ -144,16 +144,7 @@ + #define PCIE_EP_CONFIG_BASE 0xa00000 + #define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00) + #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08) +-#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4) +-#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18 +-#define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff +-#define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26 +-#define PCIE_RC_CONFIG_DCSR (PCIE_RC_CONFIG_BASE + 0xc8) +-#define PCIE_RC_CONFIG_DCSR_MPS_MASK GENMASK(7, 5) +-#define PCIE_RC_CONFIG_DCSR_MPS_256 (0x1 << 5) +-#define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc) +-#define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10) +-#define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0) ++#define PCIE_RC_CONFIG_CR (PCIE_RC_CONFIG_BASE + 0xc0) + #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c) + #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274) + #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20) diff --git a/queue-6.12/scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch b/queue-6.12/scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch new file mode 100644 index 0000000000..d38304cd1d --- /dev/null +++ b/queue-6.12/scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch @@ -0,0 +1,56 @@ +From stable+bounces-172443-greg=kroah.com@vger.kernel.org Fri Aug 22 16:52:14 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:46:41 -0400 +Subject: scsi: mpi3mr: Drop unnecessary volatile from __iomem pointers +To: stable@vger.kernel.org +Cc: Ranjan Kumar , "Martin K. Petersen" , Sasha Levin +Message-ID: <20250822144642.1269932-1-sashal@kernel.org> + +From: Ranjan Kumar + +[ Upstream commit 6853885b21cb1d7157cc14c9d30cc17141565bae ] + +The volatile qualifier is redundant for __iomem pointers. + +Cleaned up usage in mpi3mr_writeq() and sysif_regs pointer as per +Upstream compliance. + +Signed-off-by: Ranjan Kumar +Link: https://lore.kernel.org/r/20250627194539.48851-3-ranjan.kumar@broadcom.com +Signed-off-by: Martin K. Petersen +Stable-dep-of: c91e140c82eb ("scsi: mpi3mr: Serialize admin queue BAR writes on 32-bit systems") +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/scsi/mpi3mr/mpi3mr.h | 2 +- + drivers/scsi/mpi3mr/mpi3mr_fw.c | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/scsi/mpi3mr/mpi3mr.h ++++ b/drivers/scsi/mpi3mr/mpi3mr.h +@@ -1175,7 +1175,7 @@ struct mpi3mr_ioc { + char name[MPI3MR_NAME_LENGTH]; + char driver_name[MPI3MR_NAME_LENGTH]; + +- volatile struct mpi3_sysif_registers __iomem *sysif_regs; ++ struct mpi3_sysif_registers __iomem *sysif_regs; + resource_size_t sysif_regs_phys; + int bars; + u64 dma_mask; +--- a/drivers/scsi/mpi3mr/mpi3mr_fw.c ++++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c +@@ -23,12 +23,12 @@ module_param(poll_queues, int, 0444); + MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); + + #if defined(writeq) && defined(CONFIG_64BIT) +-static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) ++static inline void mpi3mr_writeq(__u64 b, void __iomem *addr) + { + writeq(b, addr); + } + #else +-static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr) ++static inline void mpi3mr_writeq(__u64 b, void __iomem *addr) + { + __u64 data_out = b; + diff --git a/queue-6.12/scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch b/queue-6.12/scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch new file mode 100644 index 0000000000..c7a106adb2 --- /dev/null +++ b/queue-6.12/scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch @@ -0,0 +1,104 @@ +From stable+bounces-172444-greg=kroah.com@vger.kernel.org Fri Aug 22 16:52:44 2025 +From: Sasha Levin +Date: Fri, 22 Aug 2025 10:46:42 -0400 +Subject: scsi: mpi3mr: Serialize admin queue BAR writes on 32-bit systems +To: stable@vger.kernel.org +Cc: Ranjan Kumar , "Martin K. Petersen" , Sasha Levin +Message-ID: <20250822144642.1269932-2-sashal@kernel.org> + +From: Ranjan Kumar + +[ Upstream commit c91e140c82eb58724c435f623702e51cc7896646 ] + +On 32-bit systems, 64-bit BAR writes to admin queue registers are +performed as two 32-bit writes. Without locking, this can cause partial +writes when accessed concurrently. + +Updated per-queue spinlocks is used to serialize these writes and prevent +race conditions. + +Fixes: 824a156633df ("scsi: mpi3mr: Base driver code") +Cc: stable@vger.kernel.org +Signed-off-by: Ranjan Kumar +Link: https://lore.kernel.org/r/20250627194539.48851-4-ranjan.kumar@broadcom.com +Signed-off-by: Martin K. Petersen +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/scsi/mpi3mr/mpi3mr.h | 4 ++++ + drivers/scsi/mpi3mr/mpi3mr_fw.c | 15 +++++++++++---- + drivers/scsi/mpi3mr/mpi3mr_os.c | 2 ++ + 3 files changed, 17 insertions(+), 4 deletions(-) + +--- a/drivers/scsi/mpi3mr/mpi3mr.h ++++ b/drivers/scsi/mpi3mr/mpi3mr.h +@@ -1131,6 +1131,8 @@ struct scmd_priv { + * @logdata_buf: Circular buffer to store log data entries + * @logdata_buf_idx: Index of entry in buffer to store + * @logdata_entry_sz: log data entry size ++ * @adm_req_q_bar_writeq_lock: Admin request queue lock ++ * @adm_reply_q_bar_writeq_lock: Admin reply queue lock + * @pend_large_data_sz: Counter to track pending large data + * @io_throttle_data_length: I/O size to track in 512b blocks + * @io_throttle_high: I/O size to start throttle in 512b blocks +@@ -1328,6 +1330,8 @@ struct mpi3mr_ioc { + u8 *logdata_buf; + u16 logdata_buf_idx; + u16 logdata_entry_sz; ++ spinlock_t adm_req_q_bar_writeq_lock; ++ spinlock_t adm_reply_q_bar_writeq_lock; + + atomic_t pend_large_data_sz; + u32 io_throttle_data_length; +--- a/drivers/scsi/mpi3mr/mpi3mr_fw.c ++++ b/drivers/scsi/mpi3mr/mpi3mr_fw.c +@@ -23,17 +23,22 @@ module_param(poll_queues, int, 0444); + MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)"); + + #if defined(writeq) && defined(CONFIG_64BIT) +-static inline void mpi3mr_writeq(__u64 b, void __iomem *addr) ++static inline void mpi3mr_writeq(__u64 b, void __iomem *addr, ++ spinlock_t *write_queue_lock) + { + writeq(b, addr); + } + #else +-static inline void mpi3mr_writeq(__u64 b, void __iomem *addr) ++static inline void mpi3mr_writeq(__u64 b, void __iomem *addr, ++ spinlock_t *write_queue_lock) + { + __u64 data_out = b; ++ unsigned long flags; + ++ spin_lock_irqsave(write_queue_lock, flags); + writel((u32)(data_out), addr); + writel((u32)(data_out >> 32), (addr + 4)); ++ spin_unlock_irqrestore(write_queue_lock, flags); + } + #endif + +@@ -2931,9 +2936,11 @@ static int mpi3mr_setup_admin_qpair(stru + (mrioc->num_admin_req); + writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries); + mpi3mr_writeq(mrioc->admin_req_dma, +- &mrioc->sysif_regs->admin_request_queue_address); ++ &mrioc->sysif_regs->admin_request_queue_address, ++ &mrioc->adm_req_q_bar_writeq_lock); + mpi3mr_writeq(mrioc->admin_reply_dma, +- &mrioc->sysif_regs->admin_reply_queue_address); ++ &mrioc->sysif_regs->admin_reply_queue_address, ++ &mrioc->adm_reply_q_bar_writeq_lock); + writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi); + writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci); + return retval; +--- a/drivers/scsi/mpi3mr/mpi3mr_os.c ++++ b/drivers/scsi/mpi3mr/mpi3mr_os.c +@@ -5251,6 +5251,8 @@ mpi3mr_probe(struct pci_dev *pdev, const + spin_lock_init(&mrioc->tgtdev_lock); + spin_lock_init(&mrioc->watchdog_lock); + spin_lock_init(&mrioc->chain_buf_lock); ++ spin_lock_init(&mrioc->adm_req_q_bar_writeq_lock); ++ spin_lock_init(&mrioc->adm_reply_q_bar_writeq_lock); + spin_lock_init(&mrioc->sas_node_lock); + spin_lock_init(&mrioc->trigger_lock); + diff --git a/queue-6.12/series b/queue-6.12/series index 166b4c5fe9..6600e62bc4 100644 --- a/queue-6.12/series +++ b/queue-6.12/series @@ -187,3 +187,19 @@ drm-amd-display-find-first-crtc-and-its-line-time-in-dce110_fill_display_configs drm-amd-display-fill-display-clock-and-vblank-time-in-dce110_fill_display_configs.patch scsi-core-fix-command-pass-through-retry-regression.patch soc-qcom-mdt_loader-fix-error-return-values-in-mdt_header_valid.patch +mptcp-remove-duplicate-sk_reset_timer-call.patch +mptcp-disable-add_addr-retransmission-when-timeout-is-0.patch +mark-xe-driver-as-broken-if-kernel-page-size-is-not-4kb.patch +pci-imx6-add-i.mx8q-pcie-endpoint-ep-support.patch +pci-imx6-add-imx8mq_ep-third-64-bit-bar-in-epc_features.patch +pci-rockchip-use-standard-pcie-definitions.patch +pci-rockchip-set-target-link-speed-to-5.0-gt-s-before-retraining.patch +iio-adc-ad7173-fix-setting-odr-in-probe.patch +scsi-mpi3mr-drop-unnecessary-volatile-from-__iomem-pointers.patch +scsi-mpi3mr-serialize-admin-queue-bar-writes-on-32-bit-systems.patch +ext4-preserve-sb_i_version-on-remount.patch +btrfs-subpage-keep-towrite-tag-until-folio-is-cleaned.patch +arm64-dts-ti-k3-am6-add-boot-phase-flag-to-support-mmc-boot.patch +arm64-dts-ti-k3-am62-add-non-removable-flag-for-emmc.patch +arm64-dts-ti-k3-am6-remove-disable-wp-for-emmc.patch +arm64-dts-ti-k3-am62-move-emmc-pinmux-to-top-level-board-file.patch