From: Greg Kroah-Hartman Date: Sun, 14 Sep 2025 16:36:10 +0000 (+0200) Subject: 6.16-stable patches X-Git-Tag: v6.1.153~34 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cede59e0a56f60fafc5891b838cc1866ae4d3a17;p=thirdparty%2Fkernel%2Fstable-queue.git 6.16-stable patches added patches: fs-resctrl-eliminate-false-positive-lockdep-warning-when-reading-snc-counters.patch hrtimers-unconditionally-update-target-cpu-base-after-offline-timer-migration.patch input-i8042-add-tuxedo-infinitybook-pro-gen10-amd-to-i8042-quirk-table.patch input-iqs7222-avoid-enabling-unused-interrupts.patch input-xpad-add-support-for-flydigi-apex-5.patch x86-cpu-topology-always-try-cpu_parse_topology_ext-on-amd-hygon.patch --- diff --git a/queue-6.16/fs-resctrl-eliminate-false-positive-lockdep-warning-when-reading-snc-counters.patch b/queue-6.16/fs-resctrl-eliminate-false-positive-lockdep-warning-when-reading-snc-counters.patch new file mode 100644 index 0000000000..756b381d54 --- /dev/null +++ b/queue-6.16/fs-resctrl-eliminate-false-positive-lockdep-warning-when-reading-snc-counters.patch @@ -0,0 +1,124 @@ +From d2e1b84c5141ff2ad465279acfc3cf943c960b78 Mon Sep 17 00:00:00 2001 +From: Reinette Chatre +Date: Mon, 8 Sep 2025 15:15:51 -0700 +Subject: fs/resctrl: Eliminate false positive lockdep warning when reading SNC counters + +From: Reinette Chatre + +commit d2e1b84c5141ff2ad465279acfc3cf943c960b78 upstream. + +Running resctrl_tests on an SNC-2 system with lockdep debugging enabled +triggers several warnings with following trace: + + WARNING: CPU: 0 PID: 1914 at kernel/cpu.c:528 lockdep_assert_cpus_held + ... + Call Trace: + __mon_event_count + ? __lock_acquire + ? __pfx___mon_event_count + mon_event_count + ? __pfx_smp_mon_event_count + smp_mon_event_count + smp_call_on_cpu_callback + +get_cpu_cacheinfo_level() called from __mon_event_count() requires CPU hotplug +lock to be held. The hotplug lock is indeed held during this time, as +confirmed by the lockdep_assert_cpus_held() within mon_event_read() that calls +mon_event_count() via IPI, but the lockdep tracking is not able to follow the +IPI. + +Fresh CPU cache information via get_cpu_cacheinfo_level() from +__mon_event_count() was added to support the fix for the issue where resctrl +inappropriately maintained links to L3 cache information that will be stale in +the case when the associated CPU goes offline. + +Keep the cacheinfo ID in struct rdt_mon_domain to ensure that resctrl does not +maintain stale cache information while CPUs can go offline. Return to using +a pointer to the L3 cache information (struct cacheinfo) in struct rmid_read, +rmid_read::ci. Initialize rmid_read::ci before the IPI where it is used. CPU +hotplug lock is held across rmid_read::ci initialization and use to ensure +that it points to accurate cache information. + +Fixes: 594902c986e2 ("x86,fs/resctrl: Remove inappropriate references to cacheinfo in the resctrl subsystem") +Signed-off-by: Reinette Chatre +Signed-off-by: Borislav Petkov (AMD) +Signed-off-by: Greg Kroah-Hartman +--- + fs/resctrl/ctrlmondata.c | 2 +- + fs/resctrl/internal.h | 4 ++-- + fs/resctrl/monitor.c | 6 ++---- + 3 files changed, 5 insertions(+), 7 deletions(-) + +diff --git a/fs/resctrl/ctrlmondata.c b/fs/resctrl/ctrlmondata.c +index d98e0d2de09f..3c39cfacb251 100644 +--- a/fs/resctrl/ctrlmondata.c ++++ b/fs/resctrl/ctrlmondata.c +@@ -625,11 +625,11 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg) + */ + list_for_each_entry(d, &r->mon_domains, hdr.list) { + if (d->ci_id == domid) { +- rr.ci_id = d->ci_id; + cpu = cpumask_any(&d->hdr.cpu_mask); + ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE); + if (!ci) + continue; ++ rr.ci = ci; + mon_event_read(&rr, r, NULL, rdtgrp, + &ci->shared_cpu_map, evtid, false); + goto checkresult; +diff --git a/fs/resctrl/internal.h b/fs/resctrl/internal.h +index 0a1eedba2b03..9a8cf6f11151 100644 +--- a/fs/resctrl/internal.h ++++ b/fs/resctrl/internal.h +@@ -98,7 +98,7 @@ struct mon_data { + * domains in @r sharing L3 @ci.id + * @evtid: Which monitor event to read. + * @first: Initialize MBM counter when true. +- * @ci_id: Cacheinfo id for L3. Only set when @d is NULL. Used when summing domains. ++ * @ci: Cacheinfo for L3. Only set when @d is NULL. Used when summing domains. + * @err: Error encountered when reading counter. + * @val: Returned value of event counter. If @rgrp is a parent resource group, + * @val includes the sum of event counts from its child resource groups. +@@ -112,7 +112,7 @@ struct rmid_read { + struct rdt_mon_domain *d; + enum resctrl_event_id evtid; + bool first; +- unsigned int ci_id; ++ struct cacheinfo *ci; + int err; + u64 val; + void *arch_mon_ctx; +diff --git a/fs/resctrl/monitor.c b/fs/resctrl/monitor.c +index f5637855c3ac..7326c28a7908 100644 +--- a/fs/resctrl/monitor.c ++++ b/fs/resctrl/monitor.c +@@ -361,7 +361,6 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr) + { + int cpu = smp_processor_id(); + struct rdt_mon_domain *d; +- struct cacheinfo *ci; + struct mbm_state *m; + int err, ret; + u64 tval = 0; +@@ -389,8 +388,7 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr) + } + + /* Summing domains that share a cache, must be on a CPU for that cache. */ +- ci = get_cpu_cacheinfo_level(cpu, RESCTRL_L3_CACHE); +- if (!ci || ci->id != rr->ci_id) ++ if (!cpumask_test_cpu(cpu, &rr->ci->shared_cpu_map)) + return -EINVAL; + + /* +@@ -402,7 +400,7 @@ static int __mon_event_count(u32 closid, u32 rmid, struct rmid_read *rr) + */ + ret = -EINVAL; + list_for_each_entry(d, &rr->r->mon_domains, hdr.list) { +- if (d->ci_id != rr->ci_id) ++ if (d->ci_id != rr->ci->id) + continue; + err = resctrl_arch_rmid_read(rr->r, d, closid, rmid, + rr->evtid, &tval, rr->arch_mon_ctx); +-- +2.51.0 + diff --git a/queue-6.16/hrtimers-unconditionally-update-target-cpu-base-after-offline-timer-migration.patch b/queue-6.16/hrtimers-unconditionally-update-target-cpu-base-after-offline-timer-migration.patch new file mode 100644 index 0000000000..0feac30d57 --- /dev/null +++ b/queue-6.16/hrtimers-unconditionally-update-target-cpu-base-after-offline-timer-migration.patch @@ -0,0 +1,73 @@ +From e895f8e29119c8c966ea794af9e9100b10becb88 Mon Sep 17 00:00:00 2001 +From: Xiongfeng Wang +Date: Tue, 5 Aug 2025 16:10:25 +0800 +Subject: hrtimers: Unconditionally update target CPU base after offline timer migration + +From: Xiongfeng Wang + +commit e895f8e29119c8c966ea794af9e9100b10becb88 upstream. + +When testing softirq based hrtimers on an ARM32 board, with high resolution +mode and NOHZ inactive, softirq based hrtimers fail to expire after being +moved away from an offline CPU: + +CPU0 CPU1 + hrtimer_start(..., HRTIMER_MODE_SOFT); +cpu_down(CPU1) ... + hrtimers_cpu_dying() + // Migrate timers to CPU0 + smp_call_function_single(CPU0, returgger_next_event); + retrigger_next_event() + if (!highres && !nohz) + return; + +As retrigger_next_event() is a NOOP when both high resolution timers and +NOHZ are inactive CPU0's hrtimer_cpu_base::softirq_expires_next is not +updated and the migrated softirq timers never expire unless there is a +softirq based hrtimer queued on CPU0 later. + +Fix this by removing the hrtimer_hres_active() and tick_nohz_active() check +in retrigger_next_event(), which enforces a full update of the CPU base. +As this is not a fast path the extra cost does not matter. + +[ tglx: Massaged change log ] + +Fixes: 5c0930ccaad5 ("hrtimers: Push pending hrtimers away from outgoing CPU earlier") +Co-developed-by: Frederic Weisbecker +Signed-off-by: Frederic Weisbecker +Signed-off-by: Xiongfeng Wang +Signed-off-by: Thomas Gleixner +Link: https://lore.kernel.org/all/20250805081025.54235-1-wangxiongfeng2@huawei.com +Signed-off-by: Greg Kroah-Hartman +--- + kernel/time/hrtimer.c | 11 +++-------- + 1 file changed, 3 insertions(+), 8 deletions(-) + +--- a/kernel/time/hrtimer.c ++++ b/kernel/time/hrtimer.c +@@ -787,10 +787,10 @@ static void retrigger_next_event(void *a + * of the next expiring timer is enough. The return from the SMP + * function call will take care of the reprogramming in case the + * CPU was in a NOHZ idle sleep. ++ * ++ * In periodic low resolution mode, the next softirq expiration ++ * must also be updated. + */ +- if (!hrtimer_hres_active(base) && !tick_nohz_active) +- return; +- + raw_spin_lock(&base->lock); + hrtimer_update_base(base); + if (hrtimer_hres_active(base)) +@@ -2295,11 +2295,6 @@ int hrtimers_cpu_dying(unsigned int dyin + &new_base->clock_base[i]); + } + +- /* +- * The migration might have changed the first expiring softirq +- * timer on this CPU. Update it. +- */ +- __hrtimer_get_next_event(new_base, HRTIMER_ACTIVE_SOFT); + /* Tell the other CPU to retrigger the next event */ + smp_call_function_single(ncpu, retrigger_next_event, NULL, 0); + diff --git a/queue-6.16/input-i8042-add-tuxedo-infinitybook-pro-gen10-amd-to-i8042-quirk-table.patch b/queue-6.16/input-i8042-add-tuxedo-infinitybook-pro-gen10-amd-to-i8042-quirk-table.patch new file mode 100644 index 0000000000..89d8404024 --- /dev/null +++ b/queue-6.16/input-i8042-add-tuxedo-infinitybook-pro-gen10-amd-to-i8042-quirk-table.patch @@ -0,0 +1,46 @@ +From 1939a9fcb80353dd8b111aa1e79c691afbde08b4 Mon Sep 17 00:00:00 2001 +From: Christoffer Sandberg +Date: Tue, 26 Aug 2025 16:26:06 +0200 +Subject: Input: i8042 - add TUXEDO InfinityBook Pro Gen10 AMD to i8042 quirk table + +From: Christoffer Sandberg + +commit 1939a9fcb80353dd8b111aa1e79c691afbde08b4 upstream. + +Occasionally wakes up from suspend with missing input on the internal +keyboard. Setting the quirks appears to fix the issue for this device as +well. + +Signed-off-by: Christoffer Sandberg +Signed-off-by: Werner Sembach +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20250826142646.13516-1-wse@tuxedocomputers.com +Signed-off-by: Dmitry Torokhov +Signed-off-by: Greg Kroah-Hartman +--- + drivers/input/serio/i8042-acpipnpio.h | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +--- a/drivers/input/serio/i8042-acpipnpio.h ++++ b/drivers/input/serio/i8042-acpipnpio.h +@@ -1155,6 +1155,20 @@ static const struct dmi_system_id i8042_ + .driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS | + SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP) + }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "XxHP4NAx"), ++ }, ++ .driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS | ++ SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP) ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "XxKK4NAx_XxSP4NAx"), ++ }, ++ .driver_data = (void *)(SERIO_QUIRK_NOMUX | SERIO_QUIRK_RESET_ALWAYS | ++ SERIO_QUIRK_NOLOOP | SERIO_QUIRK_NOPNP) ++ }, + /* + * A lot of modern Clevo barebones have touchpad and/or keyboard issues + * after suspend fixable with the forcenorestore quirk. diff --git a/queue-6.16/input-iqs7222-avoid-enabling-unused-interrupts.patch b/queue-6.16/input-iqs7222-avoid-enabling-unused-interrupts.patch new file mode 100644 index 0000000000..f19b4c290a --- /dev/null +++ b/queue-6.16/input-iqs7222-avoid-enabling-unused-interrupts.patch @@ -0,0 +1,37 @@ +From c9ddc41cdd522f2db5d492eda3df8994d928be34 Mon Sep 17 00:00:00 2001 +From: Jeff LaBundy +Date: Sun, 17 Aug 2025 19:20:22 -0500 +Subject: Input: iqs7222 - avoid enabling unused interrupts + +From: Jeff LaBundy + +commit c9ddc41cdd522f2db5d492eda3df8994d928be34 upstream. + +If a proximity event node is defined so as to specify the wake-up +properties of the touch surface, the proximity event interrupt is +enabled unconditionally. This may result in unwanted interrupts. + +Solve this problem by enabling the interrupt only if the event is +mapped to a key or switch code. + +Signed-off-by: Jeff LaBundy +Link: https://lore.kernel.org/r/aKJxxgEWpNaNcUaW@nixie71 +Cc: stable@vger.kernel.org +Signed-off-by: Dmitry Torokhov +Signed-off-by: Greg Kroah-Hartman +--- + drivers/input/misc/iqs7222.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/input/misc/iqs7222.c ++++ b/drivers/input/misc/iqs7222.c +@@ -2427,6 +2427,9 @@ static int iqs7222_parse_chan(struct iqs + if (error) + return error; + ++ if (!iqs7222->kp_type[chan_index][i]) ++ continue; ++ + if (!dev_desc->event_offset) + continue; + diff --git a/queue-6.16/input-xpad-add-support-for-flydigi-apex-5.patch b/queue-6.16/input-xpad-add-support-for-flydigi-apex-5.patch new file mode 100644 index 0000000000..20b3698446 --- /dev/null +++ b/queue-6.16/input-xpad-add-support-for-flydigi-apex-5.patch @@ -0,0 +1,40 @@ +From 47ddf62b43eced739b56422cd55e86b9b4bb7dac Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis +Date: Wed, 3 Sep 2025 18:51:14 +0200 +Subject: Input: xpad - add support for Flydigi Apex 5 + +From: Antheas Kapenekakis + +commit 47ddf62b43eced739b56422cd55e86b9b4bb7dac upstream. + +Add Flydigi Apex 5 to the list of recognized controllers. + +Reported-by: Brandon Lin +Reported-by: Sergey Belozyorcev +Signed-off-by: Antheas Kapenekakis +Link: https://lore.kernel.org/r/20250903165114.2987905-1-lkml@antheas.dev +Cc: stable@vger.kernel.org +Signed-off-by: Dmitry Torokhov +Signed-off-by: Greg Kroah-Hartman +--- + drivers/input/joystick/xpad.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/input/joystick/xpad.c ++++ b/drivers/input/joystick/xpad.c +@@ -422,6 +422,7 @@ static const struct xpad_device { + { 0x3537, 0x1010, "GameSir G7 SE", 0, XTYPE_XBOXONE }, + { 0x366c, 0x0005, "ByoWave Proteus Controller", MAP_SHARE_BUTTON, XTYPE_XBOXONE, FLAG_DELAY_INIT }, + { 0x3767, 0x0101, "Fanatec Speedster 3 Forceshock Wheel", 0, XTYPE_XBOX }, ++ { 0x37d7, 0x2501, "Flydigi Apex 5", 0, XTYPE_XBOX360 }, + { 0x413d, 0x2104, "Black Shark Green Ghost Gamepad", 0, XTYPE_XBOX360 }, + { 0xffff, 0xffff, "Chinese-made Xbox Controller", 0, XTYPE_XBOX }, + { 0x0000, 0x0000, "Generic X-Box pad", 0, XTYPE_UNKNOWN } +@@ -578,6 +579,7 @@ static const struct usb_device_id xpad_t + XPAD_XBOX360_VENDOR(0x3537), /* GameSir Controllers */ + XPAD_XBOXONE_VENDOR(0x3537), /* GameSir Controllers */ + XPAD_XBOXONE_VENDOR(0x366c), /* ByoWave controllers */ ++ XPAD_XBOX360_VENDOR(0x37d7), /* Flydigi Controllers */ + XPAD_XBOX360_VENDOR(0x413d), /* Black Shark Green Ghost Controller */ + { } + }; diff --git a/queue-6.16/series b/queue-6.16/series index 8706c65a23..d11813aeb4 100644 --- a/queue-6.16/series +++ b/queue-6.16/series @@ -110,3 +110,9 @@ mm-damon-reclaim-avoid-divide-by-zero-in-damon_reclaim_apply_parameters.patch drm-amd-display-destroy-cached-state-in-complete-callback.patch drm-amd-display-drop-dm_prepare_suspend-and-dm_complete.patch drm-amd-amdgpu-declare-isp-firmware-binary-file.patch +hrtimers-unconditionally-update-target-cpu-base-after-offline-timer-migration.patch +fs-resctrl-eliminate-false-positive-lockdep-warning-when-reading-snc-counters.patch +x86-cpu-topology-always-try-cpu_parse_topology_ext-on-amd-hygon.patch +input-iqs7222-avoid-enabling-unused-interrupts.patch +input-i8042-add-tuxedo-infinitybook-pro-gen10-amd-to-i8042-quirk-table.patch +input-xpad-add-support-for-flydigi-apex-5.patch diff --git a/queue-6.16/x86-cpu-topology-always-try-cpu_parse_topology_ext-on-amd-hygon.patch b/queue-6.16/x86-cpu-topology-always-try-cpu_parse_topology_ext-on-amd-hygon.patch new file mode 100644 index 0000000000..e507b6e091 --- /dev/null +++ b/queue-6.16/x86-cpu-topology-always-try-cpu_parse_topology_ext-on-amd-hygon.patch @@ -0,0 +1,109 @@ +From cba4262a19afae21665ee242b3404bcede5a94d7 Mon Sep 17 00:00:00 2001 +From: K Prateek Nayak +Date: Mon, 1 Sep 2025 17:04:15 +0000 +Subject: x86/cpu/topology: Always try cpu_parse_topology_ext() on AMD/Hygon + +From: K Prateek Nayak + +commit cba4262a19afae21665ee242b3404bcede5a94d7 upstream. + +Support for parsing the topology on AMD/Hygon processors using CPUID leaf 0xb +was added in + + 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available"). + +In an effort to keep all the topology parsing bits in one place, this commit +also introduced a pseudo dependency on the TOPOEXT feature to parse the CPUID +leaf 0xb. + +The TOPOEXT feature (CPUID 0x80000001 ECX[22]) advertises the support for +Cache Properties leaf 0x8000001d and the CPUID leaf 0x8000001e EAX for +"Extended APIC ID" however support for 0xb was introduced alongside the x2APIC +support not only on AMD [1], but also historically on x86 [2]. + +Similar to 0xb, the support for extended CPU topology leaf 0x80000026 too does +not depend on the TOPOEXT feature. + +The support for these leaves is expected to be confirmed by ensuring + + leaf <= {extended_}cpuid_level + +and then parsing the level 0 of the respective leaf to confirm EBX[15:0] +(LogProcAtThisLevel) is non-zero as stated in the definition of +"CPUID_Fn0000000B_EAX_x00 [Extended Topology Enumeration] +(Core::X86::Cpuid::ExtTopEnumEax0)" in Processor Programming Reference (PPR) +for AMD Family 19h Model 01h Rev B1 Vol1 [3] Sec. 2.1.15.1 "CPUID Instruction +Functions". + +This has not been a problem on baremetal platforms since support for TOPOEXT +(Fam 0x15 and later) predates the support for CPUID leaf 0xb (Fam 0x17[Zen2] +and later), however, for AMD guests on QEMU, the "x2apic" feature can be +enabled independent of the "topoext" feature where QEMU expects topology and +the initial APICID to be parsed using the CPUID leaf 0xb (especially when +number of cores > 255) which is populated independent of the "topoext" feature +flag. + +Unconditionally call cpu_parse_topology_ext() on AMD and Hygon processors to +first parse the topology using the XTOPOLOGY leaves (0x80000026 / 0xb) before +using the TOPOEXT leaf (0x8000001e). + +While at it, break down the single large comment in parse_topology_amd() to +better highlight the purpose of each CPUID leaf. + +Fixes: 3986a0a805e6 ("x86/CPU/AMD: Derive CPU topology from CPUID function 0xB when available") +Suggested-by: Naveen N Rao (AMD) +Signed-off-by: K Prateek Nayak +Signed-off-by: Borislav Petkov (AMD) +Cc: stable@vger.kernel.org # Only v6.9 and above; depends on x86 topology rewrite +Link: https://lore.kernel.org/lkml/1529686927-7665-1-git-send-email-suravee.suthikulpanit@amd.com/ [1] +Link: https://lore.kernel.org/lkml/20080818181435.523309000@linux-os.sc.intel.com/ [2] +Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 [3] +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/topology_amd.c | 25 ++++++++++++++----------- + 1 file changed, 14 insertions(+), 11 deletions(-) + +--- a/arch/x86/kernel/cpu/topology_amd.c ++++ b/arch/x86/kernel/cpu/topology_amd.c +@@ -175,27 +175,30 @@ static void topoext_fixup(struct topo_sc + + static void parse_topology_amd(struct topo_scan *tscan) + { +- bool has_topoext = false; +- + /* +- * If the extended topology leaf 0x8000_001e is available +- * try to get SMT, CORE, TILE, and DIE shifts from extended ++ * Try to get SMT, CORE, TILE, and DIE shifts from extended + * CPUID leaf 0x8000_0026 on supported processors first. If + * extended CPUID leaf 0x8000_0026 is not supported, try to +- * get SMT and CORE shift from leaf 0xb first, then try to +- * get the CORE shift from leaf 0x8000_0008. ++ * get SMT and CORE shift from leaf 0xb. If either leaf is ++ * available, cpu_parse_topology_ext() will return true. + */ +- if (cpu_feature_enabled(X86_FEATURE_TOPOEXT)) +- has_topoext = cpu_parse_topology_ext(tscan); ++ bool has_xtopology = cpu_parse_topology_ext(tscan); + + if (cpu_feature_enabled(X86_FEATURE_AMD_HTR_CORES)) + tscan->c->topo.cpu_type = cpuid_ebx(0x80000026); + +- if (!has_topoext && !parse_8000_0008(tscan)) ++ /* ++ * If XTOPOLOGY leaves (0x26/0xb) are not available, try to ++ * get the CORE shift from leaf 0x8000_0008 first. ++ */ ++ if (!has_xtopology && !parse_8000_0008(tscan)) + return; + +- /* Prefer leaf 0x8000001e if available */ +- if (parse_8000_001e(tscan, has_topoext)) ++ /* ++ * Prefer leaf 0x8000001e if available to get the SMT shift and ++ * the initial APIC ID if XTOPOLOGY leaves are not available. ++ */ ++ if (parse_8000_001e(tscan, has_xtopology)) + return; + + /* Try the NODEID MSR */