From: Nicholas Piggin Date: Mon, 12 May 2025 03:10:43 +0000 (+1000) Subject: ppc/xive: tctx_accept only lower irq line if an interrupt was presented X-Git-Tag: v10.1.0-rc0~2^2~16 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cf454eaa96e8a0c3c1de63b0f7b85542d7c5ecbf;p=thirdparty%2Fqemu.git ppc/xive: tctx_accept only lower irq line if an interrupt was presented The relationship between an interrupt signaled in the TIMA and the QEMU irq line to the processor to be 1:1, so they should be raised and lowered together and "just in case" lowering should be avoided (it could mask Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-35-npiggin@gmail.com Signed-off-by: Cédric Le Goater --- diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 119a178f2e..db26dae7db 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -95,8 +95,6 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) g_assert(tctx->regs[TM_QW2_HV_POOL + TM_PIPR] == 0); g_assert(tctx->regs[TM_QW2_HV_POOL + TM_CPPR] == 0); - qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); - if (xive_nsr_indicates_exception(sig_ring, nsr)) { uint8_t cppr = sig_regs[TM_PIPR]; uint8_t ring; @@ -117,6 +115,7 @@ uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t sig_ring) /* Clear the exception from NSR */ sig_regs[TM_NSR] = 0; + qemu_irq_lower(xive_tctx_output(tctx, sig_ring)); trace_xive_tctx_accept(tctx->cs->cpu_index, ring, regs[TM_IPB], sig_regs[TM_PIPR],