From: Greg Kroah-Hartman Date: Sun, 16 Oct 2022 16:34:05 +0000 (+0200) Subject: 6.0-stable patches X-Git-Tag: v5.4.219~72 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cf56c8b254c6dd87ae431070020d63f4f7fbb546;p=thirdparty%2Fkernel%2Fstable-queue.git 6.0-stable patches added patches: drm-i915-fix-display-problems-after-resume.patch drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch --- diff --git a/queue-6.0/drm-i915-fix-display-problems-after-resume.patch b/queue-6.0/drm-i915-fix-display-problems-after-resume.patch new file mode 100644 index 00000000000..93e8c281f9e --- /dev/null +++ b/queue-6.0/drm-i915-fix-display-problems-after-resume.patch @@ -0,0 +1,57 @@ +From 6c482c62a635aa4f534d2439fbf8afa37452b986 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= +Date: Wed, 5 Oct 2022 14:11:59 +0200 +Subject: drm/i915: Fix display problems after resume +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Thomas Hellström + +commit 6c482c62a635aa4f534d2439fbf8afa37452b986 upstream. + +Commit 39a2bd34c933 ("drm/i915: Use the vma resource as argument for gtt +binding / unbinding") introduced a regression that due to the vma resource +tracking of the binding state, dpt ptes were not correctly repopulated. +Fix this by clearing the vma resource state before repopulating. +The state will subsequently be restored by the bind_vma operation. + +Fixes: 39a2bd34c933 ("drm/i915: Use the vma resource as argument for gtt binding / unbinding") +Signed-off-by: Thomas Hellström +Link: https://patchwork.freedesktop.org/patch/msgid/20220912121957.31310-1-thomas.hellstrom@linux.intel.com +Cc: Matthew Auld +Cc: intel-gfx@lists.freedesktop.org +Cc: # v5.18+ +Reported-and-tested-by: Kevin Boulain +Tested-by: David de Sousa +Reviewed-by: Matthew Auld +Reviewed-by: Andrzej Hajda +Signed-off-by: Matthew Auld +Link: https://patchwork.freedesktop.org/patch/msgid/20221005121159.340245-1-thomas.hellstrom@linux.intel.com +(cherry picked from commit bc2472538c0d1cce334ffc9e97df0614cd2b1469) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/gt/intel_ggtt.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c ++++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c +@@ -1267,10 +1267,16 @@ bool i915_ggtt_resume_vm(struct i915_add + atomic_read(&vma->flags) & I915_VMA_BIND_MASK; + + GEM_BUG_ON(!was_bound); +- if (!retained_ptes) ++ if (!retained_ptes) { ++ /* ++ * Clear the bound flags of the vma resource to allow ++ * ptes to be repopulated. ++ */ ++ vma->resource->bound_flags = 0; + vma->ops->bind_vma(vm, NULL, vma->resource, + obj ? obj->cache_level : 0, + was_bound); ++ } + if (obj) { /* only used during resume => exclusive access */ + write_domain_objs |= fetch_and_zero(&obj->write_domain); + obj->read_domains |= I915_GEM_DOMAIN_GTT; diff --git a/queue-6.0/drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch b/queue-6.0/drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch new file mode 100644 index 00000000000..e7a9bae5f18 --- /dev/null +++ b/queue-6.0/drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch @@ -0,0 +1,53 @@ +From b2e3a1af8cce4117de06ff1a4eab0749753ede27 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 3 Oct 2022 14:15:43 +0300 +Subject: drm/i915: Fix watermark calculations for DG2 CCS+CC modifier +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit b2e3a1af8cce4117de06ff1a4eab0749753ede27 upstream. + +Take the DG2 CCS+CC modifier into account when calculating the +watermarks. Othwerwise we'll calculate the watermarks thinking this +tile-4 modifier is linear. + +The rc_surface part is actually a nop since that is not used +for any glk+ platform. + +Cc: stable@vger.kernel.org +Fixes: 680025dcc400 ("drm/i915/dg2: Add support for DG2 clear color compression") +Reviewed-by: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20221003111544.8007-6-ville.syrjala@linux.intel.com +(cherry picked from commit 334810f82024815283a6e7febd3d2de1fed6c232) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -5313,7 +5313,8 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || + modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS || +- modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; + wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; + wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || +@@ -5321,7 +5322,8 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || + modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS || +- modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; + wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); + + wp->width = width; diff --git a/queue-6.0/drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch b/queue-6.0/drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch new file mode 100644 index 00000000000..1901fa44e67 --- /dev/null +++ b/queue-6.0/drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch @@ -0,0 +1,53 @@ +From ccfa6d35f9233702c924316cdf40c05b6ce88113 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 3 Oct 2022 14:15:42 +0300 +Subject: drm/i915: Fix watermark calculations for DG2 CCS modifiers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit ccfa6d35f9233702c924316cdf40c05b6ce88113 upstream. + +Take the DG2 CCS modifiers into account when calculating the +watermarks. Othwerwise we'll calculate the watermarks thinking these +tile-4 modifiers are linear. + +The rc_surface part is actually a nop since that is not used +for any glk+ platform. + +Cc: stable@vger.kernel.org +Fixes: 4c3afa72138c ("drm/i915/dg2: Add support for DG2 render and media compression") +Reviewed-by: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20221003111544.8007-5-ville.syrjala@linux.intel.com +(cherry picked from commit f25d9f81a8e09ace4f04106995550bae1f522143) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/intel_pm.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -5311,13 +5311,17 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; + wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; + wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; + wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); + + wp->width = width; diff --git a/queue-6.0/drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch b/queue-6.0/drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch new file mode 100644 index 00000000000..e5b7265304c --- /dev/null +++ b/queue-6.0/drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch @@ -0,0 +1,50 @@ +From 070a2855900de17b1e11a0dc35af9794e80f1a28 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 3 Oct 2022 14:15:41 +0300 +Subject: drm/i915: Fix watermark calculations for gen12+ CCS+CC modifier +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 070a2855900de17b1e11a0dc35af9794e80f1a28 upstream. + +Take the gen12+ CCS+CC modifier into account when calculating the +watermarks. Othwerwise we'll calculate the watermarks thinking this +Y-tiled modifier is linear. + +The rc_surface part is actually a nop since that is not used +for any glk+ platform. + +Cc: stable@vger.kernel.org +Fixes: d1e2775e9b96 ("drm/i915/tgl: Add Clear Color support for TGL Render Decompression") +Reviewed-by: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20221003111544.8007-4-ville.syrjala@linux.intel.com +(cherry picked from commit a627455bbe50a111475d7a42beb58fa64bd96c83) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -5310,12 +5310,14 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; + wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; + wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; + wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); + + wp->width = width; diff --git a/queue-6.0/drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch b/queue-6.0/drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch new file mode 100644 index 00000000000..00033a1127b --- /dev/null +++ b/queue-6.0/drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch @@ -0,0 +1,51 @@ +From 484b2b9281000274ef7c5cb0a9ebc5da6f5c281c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 3 Oct 2022 14:15:40 +0300 +Subject: drm/i915: Fix watermark calculations for gen12+ MC CCS modifier +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 484b2b9281000274ef7c5cb0a9ebc5da6f5c281c upstream. + +Take the gen12+ MC CCS modifier into account when calculating the +watermarks. Othwerwise we'll calculate the watermarks thinking this +Y-tiled modifier is linear. + +The rc_surface part is actually a nop since that is not used +for any glk+ platform. + +v2: Split RC CCS vs. MC CCS to separate patches + +Cc: stable@vger.kernel.org +Fixes: 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") +Reviewed-by: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20221003111544.8007-3-ville.syrjala@linux.intel.com +(cherry picked from commit 91c9651425fe955b1387f3637607dda005f3f710) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -5309,11 +5309,13 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Yf_TILED || + modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; + wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; + wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; + wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); + + wp->width = width; diff --git a/queue-6.0/series b/queue-6.0/series index eadcef169be..5c6f74e3525 100644 --- a/queue-6.0/series +++ b/queue-6.0/series @@ -182,3 +182,8 @@ drm-nouveau-fix-a-use-after-free-in-nouveau_gem_prime_import_sg_table.patch drm-i915-gt-use-i915_vm_put-on-ppgtt_create-error-paths.patch drm-i915-guc-fix-revocation-of-non-persistent-contexts.patch drm-i915-fix-watermark-calculations-for-gen12-rc-ccs-modifier.patch +drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch +drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch +drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch +drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch +drm-i915-fix-display-problems-after-resume.patch