From: Pan Li Date: Fri, 20 Dec 2024 06:44:10 +0000 (+0800) Subject: RISC-V: Fix the the operand alignment for strided load/store pattern [NFC] X-Git-Tag: basepoints/gcc-16~3142 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cf59bf844037ae952f5058d0fd49e1f4f0cf907e;p=thirdparty%2Fgcc.git RISC-V: Fix the the operand alignment for strided load/store pattern [NFC] Just notice the unalignment operand for strided load/store pattern when bugfix the strided load/store memory alias, would like to make it align. gcc/ChangeLog: * config/riscv/autovec.md: Align the operand for strided load/store pattern. Signed-off-by: Pan Li --- diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 2529dc77f221..88c0f00e0ea4 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2903,7 +2903,7 @@ ;; == Strided Load/Store ;; ========================================================================= (define_expand "mask_len_strided_load_" - [(match_operand:V_VLS 0 "register_operand") + [(match_operand:V_VLS 0 "register_operand") (match_operand 1 "pmode_reg_or_0_operand") (match_operand 2 "pmode_reg_or_0_operand") (match_operand: 3 "vector_mask_operand") @@ -2919,7 +2919,7 @@ (define_expand "mask_len_strided_store_" [(match_operand 0 "pmode_reg_or_0_operand") (match_operand 1 "pmode_reg_or_0_operand") - (match_operand:V_VLS 2 "register_operand") + (match_operand:V_VLS 2 "register_operand") (match_operand: 3 "vector_mask_operand") (match_operand 4 "autovec_length_operand") (match_operand 5 "const_0_operand")]