From: Seongsu Park Date: Thu, 23 May 2024 12:21:46 +0000 (+0900) Subject: arm64: Cleanup __cpu_set_tcr_t0sz() X-Git-Tag: v6.11-rc1~217^2~1^3~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=cf938f91784f5b35d16fa9fc746a3bb03659ab50;p=thirdparty%2Flinux.git arm64: Cleanup __cpu_set_tcr_t0sz() The T0SZ field of TCR_EL1 occupies bits 0-5 of the register and encode the virtual address space translated by TTBR0_EL1. When updating the field, for example because we are switching to/from the idmap page-table, __cpu_set_tcr_t0sz() erroneously treats its 't0sz' argument as unshifted, resulting in harmless but confusing double shifts by 0 in the code. Co-developed-by: Leem ChaeHoon Signed-off-by: Leem ChaeHoon Signed-off-by: Seongsu Park Link: https://lore.kernel.org/r/20240523122146.144483-1-sgsu.park@samsung.com Signed-off-by: Catalin Marinas --- diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index c768d16b81a49..bd19f4c758b77 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) { unsigned long tcr = read_sysreg(tcr_el1); - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) + if ((tcr & TCR_T0SZ_MASK) == t0sz) return; tcr &= ~TCR_T0SZ_MASK; - tcr |= t0sz << TCR_T0SZ_OFFSET; + tcr |= t0sz; write_sysreg(tcr, tcr_el1); isb(); }