From: Julian Seward Date: Mon, 1 May 2006 02:14:17 +0000 (+0000) Subject: Counterpart to r1605: in the ppc insn selector, don't use the bits X-Git-Tag: svn/VALGRIND_3_2_3^2~72 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d03eff3189a629dd43d8946b875c5d597f863155;p=thirdparty%2Fvalgrind.git Counterpart to r1605: in the ppc insn selector, don't use the bits VexArchInfo.hwcaps to distinguish ppc32 and ppc64. Instead pass the host arch around. And associated plumbing. git-svn-id: svn://svn.valgrind.org/vex/trunk@1606 --- diff --git a/VEX/priv/host-amd64/hdefs.h b/VEX/priv/host-amd64/hdefs.h index 621e4dfb98..a321793bfb 100644 --- a/VEX/priv/host-amd64/hdefs.h +++ b/VEX/priv/host-amd64/hdefs.h @@ -718,7 +718,7 @@ extern Int emit_AMD64Instr ( UChar* buf, Int nbuf, AMD64Instr*, extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset, Bool ); extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset, Bool ); extern void getAllocableRegs_AMD64 ( Int*, HReg** ); -extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArchInfo* ); +extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArch, VexArchInfo* ); #endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */ diff --git a/VEX/priv/host-amd64/isel.c b/VEX/priv/host-amd64/isel.c index 1b7f314338..c19542c691 100644 --- a/VEX/priv/host-amd64/isel.c +++ b/VEX/priv/host-amd64/isel.c @@ -3760,7 +3760,8 @@ static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk ) /* Translate an entire BB to amd64 code. */ -HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArchInfo* archinfo_host ) +HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArch arch_host, + VexArchInfo* archinfo_host ) { Int i, j; HReg hreg, hregHI; @@ -3768,6 +3769,7 @@ HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArchInfo* archinfo_host ) UInt hwcaps_host = archinfo_host->hwcaps; /* sanity ... */ + vassert(arch_host == VexArchAMD64); vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_AMD64_SSE3))); /* Make up an initial environment to use. */ diff --git a/VEX/priv/host-ppc/hdefs.h b/VEX/priv/host-ppc/hdefs.h index dc2a60fd92..7aa8f22766 100644 --- a/VEX/priv/host-ppc/hdefs.h +++ b/VEX/priv/host-ppc/hdefs.h @@ -838,7 +838,7 @@ extern Int emit_PPCInstr ( UChar* buf, Int nbuf, PPCInstr*, extern PPCInstr* genSpill_PPC ( HReg rreg, UShort offsetB, Bool mode64 ); extern PPCInstr* genReload_PPC ( HReg rreg, UShort offsetB, Bool mode64 ); extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 ); -extern HInstrArray* iselBB_PPC ( IRBB*, VexArchInfo* ); +extern HInstrArray* iselBB_PPC ( IRBB*, VexArch, VexArchInfo* ); #endif /* ndef __LIBVEX_HOST_PPC_HDEFS_H */ diff --git a/VEX/priv/host-ppc/isel.c b/VEX/priv/host-ppc/isel.c index bfbe660822..de63a4a1b9 100644 --- a/VEX/priv/host-ppc/isel.c +++ b/VEX/priv/host-ppc/isel.c @@ -3839,33 +3839,31 @@ static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk ) /* Translate an entire BB to ppc code. */ -HInstrArray* iselBB_PPC ( IRBB* bb, VexArchInfo* archinfo_host ) +HInstrArray* iselBB_PPC ( IRBB* bb, VexArch arch_host, + VexArchInfo* archinfo_host ) { Int i, j; HReg hreg, hregHI; ISelEnv* env; UInt hwcaps_host = archinfo_host->hwcaps; Bool mode64 = False; - Bool is32, is64; UInt mask32, mask64; - /* Figure out whether we're being ppc32 or ppc64 today. */ + vassert(arch_host == VexArchPPC32 || arch_host == VexArchPPC64); + mode64 = arch_host == VexArchPPC64; + + /* do some sanity checks */ mask32 = VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V | VEX_HWCAPS_PPC32_FX | VEX_HWCAPS_PPC32_GX; - is32 = (hwcaps_host & mask32) > 0; - mask64 = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX | VEX_HWCAPS_PPC64_GX; - is64 = (hwcaps_host & mask64) > 0; - - if (is32 && !is64) - mode64 = False; - else if (is64 && !is32) - mode64 = True; - else - vpanic("iselBB_PPC: illegal subarch"); + if (mode64) { + vassert((hwcaps_host & mask32) == 0); + } else { + vassert((hwcaps_host & mask64) == 0); + } /* Make up an initial environment to use. */ env = LibVEX_Alloc(sizeof(ISelEnv)); diff --git a/VEX/priv/host-x86/hdefs.h b/VEX/priv/host-x86/hdefs.h index 5bc8ec6dbf..35200808b6 100644 --- a/VEX/priv/host-x86/hdefs.h +++ b/VEX/priv/host-x86/hdefs.h @@ -665,7 +665,7 @@ extern Int emit_X86Instr ( UChar* buf, Int nbuf, X86Instr*, extern X86Instr* genSpill_X86 ( HReg rreg, Int offset, Bool ); extern X86Instr* genReload_X86 ( HReg rreg, Int offset, Bool ); extern void getAllocableRegs_X86 ( Int*, HReg** ); -extern HInstrArray* iselBB_X86 ( IRBB*, VexArchInfo* ); +extern HInstrArray* iselBB_X86 ( IRBB*, VexArch, VexArchInfo* ); #endif /* ndef __LIBVEX_HOST_X86_HDEFS_H */ diff --git a/VEX/priv/host-x86/isel.c b/VEX/priv/host-x86/isel.c index 0d55f30a31..86c4d7df4e 100644 --- a/VEX/priv/host-x86/isel.c +++ b/VEX/priv/host-x86/isel.c @@ -3604,7 +3604,8 @@ static void iselNext ( ISelEnv* env, IRExpr* next, IRJumpKind jk ) /* Translate an entire BB to x86 code. */ -HInstrArray* iselBB_X86 ( IRBB* bb, VexArchInfo* archinfo_host ) +HInstrArray* iselBB_X86 ( IRBB* bb, VexArch arch_host, + VexArchInfo* archinfo_host ) { Int i, j; HReg hreg, hregHI; @@ -3612,6 +3613,7 @@ HInstrArray* iselBB_X86 ( IRBB* bb, VexArchInfo* archinfo_host ) UInt hwcaps_host = archinfo_host->hwcaps; /* sanity ... */ + vassert(arch_host == VexArchX86); vassert(0 == (hwcaps_host & ~(VEX_HWCAPS_X86_SSE1 |VEX_HWCAPS_X86_SSE2 |VEX_HWCAPS_X86_SSE3))); diff --git a/VEX/priv/main/vex_main.c b/VEX/priv/main/vex_main.c index b26fc012f1..db53719771 100644 --- a/VEX/priv/main/vex_main.c +++ b/VEX/priv/main/vex_main.c @@ -193,7 +193,7 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) HInstr* (*genReload) ( HReg, Int, Bool ); void (*ppInstr) ( HInstr*, Bool ); void (*ppReg) ( HReg ); - HInstrArray* (*iselBB) ( IRBB*, VexArchInfo* ); + HInstrArray* (*iselBB) ( IRBB*, VexArch, VexArchInfo* ); Int (*emit) ( UChar*, Int, HInstr*, Bool, void* ); IRExpr* (*specHelper) ( HChar*, IRExpr** ); Bool (*preciseMemExnsFn) ( Int, Int ); @@ -558,7 +558,7 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) " Instruction selection " "------------------------\n"); - vcode = iselBB ( irbb, &vta->archinfo_host ); + vcode = iselBB ( irbb, vta->arch_host, &vta->archinfo_host ); vexAllocSanityCheck();