From: Greg Kroah-Hartman Date: Wed, 3 Jul 2019 07:25:05 +0000 (+0200) Subject: 5.1-stable patches X-Git-Tag: v5.1.16~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d0f506ba82ea938c117d79f921661728121ee2ee;p=thirdparty%2Fkernel%2Fstable-queue.git 5.1-stable patches added patches: arm64-insn-fix-ldadd-instruction-encoding.patch --- diff --git a/queue-5.1/arm64-insn-fix-ldadd-instruction-encoding.patch b/queue-5.1/arm64-insn-fix-ldadd-instruction-encoding.patch new file mode 100644 index 00000000000..532f9383b97 --- /dev/null +++ b/queue-5.1/arm64-insn-fix-ldadd-instruction-encoding.patch @@ -0,0 +1,45 @@ +From c5e2edeb01ae9ffbdde95bdcdb6d3614ba1eb195 Mon Sep 17 00:00:00 2001 +From: Jean-Philippe Brucker +Date: Fri, 24 May 2019 13:52:19 +0100 +Subject: arm64: insn: Fix ldadd instruction encoding + +From: Jean-Philippe Brucker + +commit c5e2edeb01ae9ffbdde95bdcdb6d3614ba1eb195 upstream. + +GCC 8.1.0 reports that the ldadd instruction encoding, recently added to +insn.c, doesn't match the mask and couldn't possibly be identified: + + linux/arch/arm64/include/asm/insn.h: In function 'aarch64_insn_is_ldadd': + linux/arch/arm64/include/asm/insn.h:280:257: warning: bitwise comparison always evaluates to false [-Wtautological-compare] + +Bits [31:30] normally encode the size of the instruction (1 to 8 bytes) +and the current instruction value only encodes the 4- and 8-byte +variants. At the moment only the BPF JIT needs this instruction, and +doesn't require the 1- and 2-byte variants, but to be consistent with +our other ldr and str instruction encodings, clear the size field in the +insn value. + +Fixes: 34b8ab091f9ef57a ("bpf, arm64: use more scalable stadd over ldxr / stxr loop in xadd") +Acked-by: Daniel Borkmann +Reported-by: Kuninori Morimoto +Signed-off-by: Yoshihiro Shimoda +Signed-off-by: Jean-Philippe Brucker +Signed-off-by: Will Deacon +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/include/asm/insn.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/include/asm/insn.h ++++ b/arch/arm64/include/asm/insn.h +@@ -277,7 +277,7 @@ __AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0 + __AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000) + __AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000) + __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) +-__AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0xB8200000) ++__AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000) + __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) + __AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000) + __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000) diff --git a/queue-5.1/series b/queue-5.1/series index bbe9dc0cd35..7ddb67043b5 100644 --- a/queue-5.1/series +++ b/queue-5.1/series @@ -53,3 +53,4 @@ futex-update-comments-and-docs-about-return-values-of-arch-futex-code.patch rdma-directly-cast-the-sockaddr-union-to-sockaddr.patch fanotify-update-connector-fsid-cache-on-add-mark.patch tipc-pass-tunnel-dev-as-null-to-udp_tunnel-6-_xmit_skb.patch +arm64-insn-fix-ldadd-instruction-encoding.patch