From: Krzysztof Kozlowski Date: Mon, 27 Jan 2025 13:21:04 +0000 (+0100) Subject: dt-bindings: display/msm/dsi-phy: Add header with exposed clock IDs X-Git-Tag: v6.15-rc1~120^2~11^2~78 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d1f28e30a525107cd3b7927b73c69fbab9e826a5;p=thirdparty%2Flinux.git dt-bindings: display/msm/dsi-phy: Add header with exposed clock IDs DSI phys, from earliest (28 nm) up to newest (3 nm) generation, provide two clocks. The respective clock ID is used by drivers and DTS, so it should be documented as explicit ABI. Signed-off-by: Krzysztof Kozlowski Acked-by: Stephen Boyd Acked-by: Dmitry Baryshkov Patchwork: https://patchwork.freedesktop.org/patch/634146/ Link: https://lore.kernel.org/r/20250127132105.107138-1-krzysztof.kozlowski@linaro.org Signed-off-by: Dmitry Baryshkov --- diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml index 6b57ce41c95f2..d0ce85a08b6dc 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml @@ -15,6 +15,8 @@ description: properties: "#clock-cells": const: 1 + description: + See include/dt-bindings/clock/qcom,dsi-phy-28nm.h for clock IDs. "#phy-cells": const: 0 diff --git a/MAINTAINERS b/MAINTAINERS index 43b55429f0fc9..9f29ec77a6546 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7392,6 +7392,7 @@ T: git https://gitlab.freedesktop.org/drm/msm.git F: Documentation/devicetree/bindings/display/msm/ F: drivers/gpu/drm/ci/xfails/msm* F: drivers/gpu/drm/msm/ +F: include/dt-bindings/clock/qcom,dsi-phy-28nm.h F: include/uapi/drm/msm_drm.h DRM DRIVER FOR NOVATEK NT35510 PANELS diff --git a/include/dt-bindings/clock/qcom,dsi-phy-28nm.h b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h new file mode 100644 index 0000000000000..ab94d58377a1c --- /dev/null +++ b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H +#define _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 + +#endif