From: Nicholas Piggin Date: Mon, 12 May 2025 03:10:28 +0000 (+1000) Subject: pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL X-Git-Tag: v10.1.0-rc0~2^2~31 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d273abbfba47ef47e331dc22731c7d2a15e95c9a;p=thirdparty%2Fqemu.git pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC register, so don't clear it on read. Don't bother clearing the reads-as-zero CONFLICT bit because it's masked at write already. Signed-off-by: Nicholas Piggin Reviewed-by: Glenn Miles Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-20-npiggin@gmail.com Signed-off-by: Cédric Le Goater --- diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 9d53537e3e..e15f414d0b 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1329,7 +1329,6 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset, case VC_ENDC_WATCH2_SPEC: case VC_ENDC_WATCH3_SPEC: watch_engine = (offset - VC_ENDC_WATCH0_SPEC) >> 6; - xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT); pnv_xive2_endc_cache_watch_release(xive, watch_engine); val = xive->vc_regs[reg]; break;