From: Siddhesh Poyarekar Date: Fri, 11 Sep 2020 03:48:09 +0000 (+0530) Subject: [Morello] Allow lo12 relocations for alternate base ld/st X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d2beed31c500be36f991a0a7f5596665979b054b;p=thirdparty%2Fbinutils-gdb.git [Morello] Allow lo12 relocations for alternate base ld/st This brings feature parity between the regular, Morello and alternate base load/store instructions. bfd/ChangeLog: 2020-10-20 Siddhesh Poyarekar * elfxx-aarch64.c (reencode_ldst_pos_imm): Support loads and stores with alternate base. gas/ChangeLog: 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (ldst_lo12_determine_real_reloc_type): Support alternate base loads and stores. (parse_operands): Support relocations for alternate base address operands. * testsuite/gas/aarch64/morello-ldst-reloc.d: New file. * testsuite/gas/aarch64/morello-ldst-reloc.s: New file. --- diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 7a1c8b737bf..bf9e320b44b 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,8 @@ +2020-10-20 Siddhesh Poyarekar + + * elfxx-aarch64.c (reencode_ldst_pos_imm): Support loads and + stores with alternate base. + 2020-10-20 Siddhesh Poyarekar * elfnn-aarch64.c (elfNN_aarch64_howto_table, diff --git a/bfd/elfxx-aarch64.c b/bfd/elfxx-aarch64.c index d16a0578608..6a905b92900 100644 --- a/bfd/elfxx-aarch64.c +++ b/bfd/elfxx-aarch64.c @@ -67,7 +67,21 @@ _bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm, uint32_t c64) static inline uint32_t reencode_ldst_pos_imm (uint32_t insn, uint32_t imm) { - return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10); + uint32_t mask, pos; + + /* Alternate base load/store instructions have a 9-bit offset starting from + bit 12. */ + if ((insn & 0xf0000000) == 0x80000000) + { + mask = MASK (9); + pos = 12; + } + else + { + mask = MASK (12); + pos = 10; + } + return (insn & ~(mask << pos)) | ((imm & mask) << pos); } /* Encode the 26-bit offset of unconditional branch. */ diff --git a/gas/ChangeLog b/gas/ChangeLog index 324e6b65324..86b92bb467a 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,12 @@ +2020-10-20 Siddhesh Poyarekar + + * config/tc-aarch64.c (ldst_lo12_determine_real_reloc_type): + Support alternate base loads and stores. + (parse_operands): Support relocations for alternate base + address operands. + * testsuite/gas/aarch64/morello-ldst-reloc.d: New file. + * testsuite/gas/aarch64/morello-ldst-reloc.s: New file. + 2020-10-20 Siddhesh Poyarekar * config/tc-aarch64.c (s_aarch64_capinit): New function. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index fd288bc3b02..55e0358bc11 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5702,7 +5702,8 @@ ldst_lo12_determine_real_reloc_type (void) == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12) || (inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC)); - gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12); + gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12 + || inst.base.opcode->operands[1] == AARCH64_OPND_CAPADDR_UIMM9); if (opd1_qlf == AARCH64_OPND_QLF_NIL) opd1_qlf = @@ -6848,11 +6849,6 @@ addr_simm: case AARCH64_OPND_CAPADDR_UIMM9: po_misc_or_fail (parse_cap_address (&str, info, opcode->iclass)); - if (inst.reloc.type != BFD_RELOC_UNUSED) - { - set_syntax_error (_("relocation not allowed")); - goto failure; - } goto addr_uimm; case AARCH64_OPND_ADDR_UIMM12: @@ -6875,7 +6871,18 @@ addr_uimm: == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12) || (inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC)) - inst.reloc.type = ldst_lo12_determine_real_reloc_type (); + { + /* The altbase ldrb instruction does not have enough range to + accommodate a LO12 relocation. */ + if (opcode->flags & F_NOSHIFT && opcode->iclass == ldst_altbase) + { + set_syntax_error (_("relocation not allowed")); + goto failure; + } + + inst.reloc.type = ldst_lo12_determine_real_reloc_type (); + } + /* Leave qualifier to be determined by libopcodes. */ break; diff --git a/gas/testsuite/gas/aarch64/morello-ldst-reloc.d b/gas/testsuite/gas/aarch64/morello-ldst-reloc.d new file mode 100644 index 00000000000..7e4fcf4f079 --- /dev/null +++ b/gas/testsuite/gas/aarch64/morello-ldst-reloc.d @@ -0,0 +1,21 @@ +#as: -march=morello+c64 +#objdump: -dr + +.*: file format .* + + +Disassembly of section \.text: + +.* <_start>: +.*: c2400042 ldr c2, \[c2\] + .*: R_AARCH64_LDST128_ABS_LO12_NC \.data\+0x10 +.*: 82600042 ldr c2, \[x2\] + .*: R_AARCH64_LDST128_ABS_LO12_NC \.data\+0x10 +.*: 82600c42 ldr x2, \[x2\] + .*: R_AARCH64_LDST64_ABS_LO12_NC \.data\+0x10 +.*: 82600842 ldr w2, \[x2\] + .*: R_AARCH64_LDST32_ABS_LO12_NC \.data\+0x10 + +.* : +.*: 02000000 add c0, c0, #0x0 + .*: R_AARCH64_ADD_ABS_LO12_NC ptr diff --git a/gas/testsuite/gas/aarch64/morello-ldst-reloc.s b/gas/testsuite/gas/aarch64/morello-ldst-reloc.s new file mode 100644 index 00000000000..2aa4bbe3ec7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/morello-ldst-reloc.s @@ -0,0 +1,20 @@ +.data +pad: + .word 0x42 +.align 4 +cap: + .capinit pad + .8byte 0x0 + .8byte 0x0 + +.text +.globl _start +.type _start STT_FUNC +_start: + ldr c2, [c2, :lo12:cap] + ldr c2, [x2, :lo12:cap] + ldr x2, [x2, :lo12:cap] + ldr w2, [x2, :lo12:cap] + +add: + add c0, c0, :lo12:ptr