From: Jamin Lin <jamin_lin@aspeedtech.com>
Date: Tue, 29 Oct 2024 09:17:24 +0000 (+0800)
Subject: hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600
X-Git-Tag: v9.2.0-rc0~21^2~3
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d3d6def468ff18b387ced3de79c0339aa7c1c78d;p=thirdparty%2Fqemu.git

hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600

According to the datasheet of AST2600 description, interrupt status set by HW
and clear to "0" by software writing "1" on the specific bit.

Therefore, if firmware set the specific bit "1" in the interrupt status
register(0x34), the specific bit of "s->irq_sts" should be cleared 0.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on the AST2600")
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
---

diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 5af268ea9eb..149f7cc5a6a 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -580,7 +580,7 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
 
     switch (offset) {
     case 0x34:
-        s->irq_sts &= tv;
+        s->irq_sts &= ~tv;
         break;
     case 0x3C:
         aspeed_timer_set_ctrl(s, s->ctrl & ~tv);