From: Roger Sayle <roger@nextmovesoftware.com>
Date: Tue, 5 Jul 2022 16:55:53 +0000 (+0100)
Subject: PR rtl-optimization/96692: ((A|B)^C)^A using andn with -mbmi on x86.
X-Git-Tag: basepoints/gcc-14~5700
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d458c53a6f37c8c49aa854d12e6867b4d914555f;p=thirdparty%2Fgcc.git

PR rtl-optimization/96692: ((A|B)^C)^A using andn with -mbmi on x86.

This patch addresses PR rtl-optimization/96692 on x86_64, by providing
a set of combine splitters to convert the three operation ((A|B)^C)^D
into a two operation sequence using andn when either A or B is the same
register as C or D.  This is essentially a reassociation problem that's
only a win if the target supports an and-not instruction (as with -mbmi).

Hence for the new test case:

int f(int a, int b, int c)
{
    return (a ^ b) ^ (a | c);
}

GCC on x86_64-pc-linux-gnu wth -O2 -mbmi would previously generate:

        xorl    %edi, %esi
        orl     %edx, %edi
        movl    %esi, %eax
        xorl    %edi, %eax
        ret

but with this patch now generates:

        andn    %edx, %edi, %eax
        xorl    %esi, %eax
        ret

2022-07-05  Roger Sayle  <roger@nextmovesoftware.com>
	    Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog
	PR rtl-optimization/96692
	* config/i386/i386.md (define_split): Split ((A | B) ^ C) ^ D
	as (X & ~Y) ^ Z on target BMI when either C or D is A or B.

gcc/testsuite/ChangeLog
	PR rtl-optimization/96692
	* gcc.target/i386/bmi-andn-4.c: New test case.
---

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 20c3b9a4122..d11475489fc 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -10522,6 +10522,82 @@
    (set (match_dup 0) (match_op_dup 1
                         [(and:SI (match_dup 3) (match_dup 2))
 			 (const_int 0)]))])
+
+;; Variant 1 of 4: Split ((A | B) ^ A) ^ C as (B & ~A) ^ C.
+(define_split
+  [(set (match_operand:SWI48 0 "register_operand")
+	(xor:SWI48
+	   (xor:SWI48
+	      (ior:SWI48 (match_operand:SWI48 1 "register_operand")
+			 (match_operand:SWI48 2 "nonimmediate_operand"))
+	      (match_dup 1))
+	   (match_operand:SWI48 3 "nonimmediate_operand")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_BMI"
+  [(parallel
+      [(set (match_dup 4) (and:SWI48 (not:SWI48 (match_dup 1)) (match_dup 2)))
+       (clobber (reg:CC FLAGS_REG))])
+   (parallel
+      [(set (match_dup 0) (xor:SWI48 (match_dup 4) (match_dup 3)))
+       (clobber (reg:CC FLAGS_REG))])]
+  "operands[4] = gen_reg_rtx (<MODE>mode);")
+
+;; Variant 2 of 4: Split ((A | B) ^ B) ^ C as (A & ~B) ^ C.
+(define_split
+  [(set (match_operand:SWI48 0 "register_operand")
+	(xor:SWI48
+	   (xor:SWI48
+	      (ior:SWI48 (match_operand:SWI48 1 "register_operand")
+			 (match_operand:SWI48 2 "register_operand"))
+	      (match_dup 2))
+	   (match_operand:SWI48 3 "nonimmediate_operand")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_BMI"
+  [(parallel
+      [(set (match_dup 4) (and:SWI48 (not:SWI48 (match_dup 2)) (match_dup 1)))
+       (clobber (reg:CC FLAGS_REG))])
+   (parallel
+      [(set (match_dup 0) (xor:SWI48 (match_dup 4) (match_dup 3)))
+       (clobber (reg:CC FLAGS_REG))])]
+  "operands[4] = gen_reg_rtx (<MODE>mode);")
+
+;; Variant 3 of 4: Split ((A | B) ^ C) ^ A as (B & ~A) ^ C.
+(define_split
+  [(set (match_operand:SWI48 0 "register_operand")
+	(xor:SWI48
+	   (xor:SWI48
+	      (ior:SWI48 (match_operand:SWI48 1 "register_operand")
+			 (match_operand:SWI48 2 "nonimmediate_operand"))
+	      (match_operand:SWI48 3 "nonimmediate_operand"))
+	   (match_dup 1)))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_BMI"
+  [(parallel
+      [(set (match_dup 4) (and:SWI48 (not:SWI48 (match_dup 1)) (match_dup 2)))
+       (clobber (reg:CC FLAGS_REG))])
+   (parallel
+      [(set (match_dup 0) (xor:SWI48 (match_dup 4) (match_dup 3)))
+       (clobber (reg:CC FLAGS_REG))])]
+  "operands[4] = gen_reg_rtx (<MODE>mode);")
+
+;; Variant 4 of 4: Split ((A | B) ^ C) ^ B as (A & ~B) ^ C.
+(define_split
+  [(set (match_operand:SWI48 0 "register_operand")
+	(xor:SWI48
+	   (xor:SWI48
+	      (ior:SWI48 (match_operand:SWI48 1 "register_operand")
+			 (match_operand:SWI48 2 "register_operand"))
+	      (match_operand:SWI48 3 "nonimmediate_operand"))
+	   (match_dup 2)))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_BMI"
+  [(parallel
+      [(set (match_dup 4) (and:SWI48 (not:SWI48 (match_dup 2)) (match_dup 1)))
+       (clobber (reg:CC FLAGS_REG))])
+   (parallel
+      [(set (match_dup 0) (xor:SWI48 (match_dup 4) (match_dup 3)))
+       (clobber (reg:CC FLAGS_REG))])]
+  "operands[4] = gen_reg_rtx (<MODE>mode);")
 
 ;; Logical inclusive and exclusive OR instructions
 
diff --git a/gcc/testsuite/gcc.target/i386/bmi-andn-4.c b/gcc/testsuite/gcc.target/i386/bmi-andn-4.c
new file mode 100644
index 00000000000..fb895298694
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/bmi-andn-4.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mbmi" } */
+
+int f(int a, int b, int c)
+{
+    return (a ^ b) ^ (a | c);
+}
+
+/* { dg-final { scan-assembler "andn\[ \\t\]+" } } */