From: Linus Torvalds <torvalds@linux-foundation.org>
Date: Wed, 8 Nov 2023 17:21:18 +0000 (-0800)
Subject: Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel... 
X-Git-Tag: v6.7-rc1~38
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d46392bbf5c6ce594669f00b8177f0b34e983f90;p=thirdparty%2Fkernel%2Flinux.git

Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:

 - Support for cbo.zero in userspace

 - Support for CBOs on ACPI-based systems

 - A handful of improvements for the T-Head cache flushing ops

 - Support for software shadow call stacks

 - Various cleanups and fixes

* tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (31 commits)
  RISC-V: hwprobe: Fix vDSO SIGSEGV
  riscv: configs: defconfig: Enable configs required for RZ/Five SoC
  riscv: errata: prefix T-Head mnemonics with th.
  riscv: put interrupt entries into .irqentry.text
  riscv: mm: Update the comment of CONFIG_PAGE_OFFSET
  riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause
  riscv/mm: Fix the comment for swap pte format
  RISC-V: clarify the QEMU workaround in ISA parser
  riscv: correct pt_level name via pgtable_l5/4_enabled
  RISC-V: Provide pgtable_l5_enabled on rv32
  clocksource: timer-riscv: Increase rating of clock_event_device for Sstc
  clocksource: timer-riscv: Don't enable/disable timer interrupt
  lkdtm: Fix CFI_BACKWARD on RISC-V
  riscv: Use separate IRQ shadow call stacks
  riscv: Implement Shadow Call Stack
  riscv: Move global pointer loading to a macro
  riscv: Deduplicate IRQ stack switching
  riscv: VMAP_STACK overflow detection thread-safe
  RISC-V: cacheflush: Initialize CBO variables on ACPI systems
  RISC-V: ACPI: RHCT: Add function to get CBO block sizes
  ...
---

d46392bbf5c6ce594669f00b8177f0b34e983f90
diff --cc arch/riscv/kernel/irq.c
index 9cc0a76692715,7bfea97ee7e7e..9ceda02507cae
--- a/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@@ -60,41 -79,23 +79,23 @@@ static void init_irq_stacks(void
  }
  #endif /* CONFIG_VMAP_STACK */
  
 -#ifdef CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK
 +#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
+ static void ___do_softirq(struct pt_regs *regs)
+ {
+ 	__do_softirq();
+ }
+ 
  void do_softirq_own_stack(void)
  {
- #ifdef CONFIG_IRQ_STACKS
- 	if (on_thread_stack()) {
- 		ulong *sp = per_cpu(irq_stack_ptr, smp_processor_id())
- 					+ IRQ_STACK_SIZE/sizeof(ulong);
- 		__asm__ __volatile(
- 		"addi	sp, sp, -"RISCV_SZPTR  "\n"
- 		REG_S"  ra, (sp)		\n"
- 		"addi	sp, sp, -"RISCV_SZPTR  "\n"
- 		REG_S"  s0, (sp)		\n"
- 		"addi	s0, sp, 2*"RISCV_SZPTR "\n"
- 		"move	sp, %[sp]		\n"
- 		"call	__do_softirq		\n"
- 		"addi	sp, s0, -2*"RISCV_SZPTR"\n"
- 		REG_L"  s0, (sp)		\n"
- 		"addi	sp, sp, "RISCV_SZPTR   "\n"
- 		REG_L"  ra, (sp)		\n"
- 		"addi	sp, sp, "RISCV_SZPTR   "\n"
- 		:
- 		: [sp] "r" (sp)
- 		: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
- 		  "t0", "t1", "t2", "t3", "t4", "t5", "t6",
- #ifndef CONFIG_FRAME_POINTER
- 		  "s0",
- #endif
- 		  "memory");
- 	} else
- #endif
+ 	if (on_thread_stack())
+ 		call_on_irq_stack(NULL, ___do_softirq);
+ 	else
  		__do_softirq();
  }
 -#endif /* CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK */
 +#endif /* CONFIG_SOFTIRQ_ON_OWN_STACK */
  
  #else
+ static void init_irq_scs(void) {}
  static void init_irq_stacks(void) {}
  #endif /* CONFIG_IRQ_STACKS */