From: Greg Kroah-Hartman Date: Sun, 10 Apr 2016 18:30:53 +0000 (-0700) Subject: 3.14-stable patches X-Git-Tag: v4.5.1~7 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d47e793b30ac5c9c50bf316cdd635d7c38067cdd;p=thirdparty%2Fkernel%2Fstable-queue.git 3.14-stable patches added patches: 0004-perf-x86-intel-Use-PAGE_SIZE-for-PEBS-buffer-size-on.patch 0005-perf-x86-intel-Fix-PEBS-data-source-interpretation-o.patch --- diff --git a/queue-3.14/0004-perf-x86-intel-Use-PAGE_SIZE-for-PEBS-buffer-size-on.patch b/queue-3.14/0004-perf-x86-intel-Use-PAGE_SIZE-for-PEBS-buffer-size-on.patch new file mode 100644 index 00000000000..6082f0528a5 --- /dev/null +++ b/queue-3.14/0004-perf-x86-intel-Use-PAGE_SIZE-for-PEBS-buffer-size-on.patch @@ -0,0 +1,97 @@ +From 3135a66b768c5ee84c8a98b21d0330dc1c1234b4 Mon Sep 17 00:00:00 2001 +From: Jiri Olsa +Date: Tue, 1 Mar 2016 20:03:52 +0100 +Subject: perf/x86/intel: Use PAGE_SIZE for PEBS buffer size on Core2 + +From: Jiri Olsa + +commit 3135a66b768c5ee84c8a98b21d0330dc1c1234b4 upstream. + +Using PAGE_SIZE buffers makes the WRMSR to PERF_GLOBAL_CTRL in +intel_pmu_enable_all() mysteriously hang on Core2. As a workaround, we +don't do this. + +The hard lockup is easily triggered by running 'perf test attr' +repeatedly. Most of the time it gets stuck on sample session with +small periods. + + # perf test attr -vv + 14: struct perf_event_attr setup : + --- start --- + ... + 'PERF_TEST_ATTR=/tmp/tmpuEKz3B /usr/bin/perf record -o /tmp/tmpuEKz3B/perf.data -c 123 kill >/dev/null 2>&1' ret 1 + +Reported-by: Arnaldo Carvalho de Melo +Signed-off-by: Jiri Olsa +Signed-off-by: Peter Zijlstra (Intel) +Reviewed-by: Andi Kleen +Cc: Alexander Shishkin +Cc: Jiri Olsa +Cc: Kan Liang +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Stephane Eranian +Cc: Thomas Gleixner +Cc: Vince Weaver +Cc: Wang Nan +Link: http://lkml.kernel.org/r/20160301190352.GA8355@krava.redhat.com +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/perf_event.h | 1 + + arch/x86/kernel/cpu/perf_event_intel_ds.c | 13 +++++++++++-- + 2 files changed, 12 insertions(+), 2 deletions(-) + +--- a/arch/x86/kernel/cpu/perf_event.h ++++ b/arch/x86/kernel/cpu/perf_event.h +@@ -445,6 +445,7 @@ struct x86_pmu { + pebs_active :1, + pebs_broken :1; + int pebs_record_size; ++ int pebs_buffer_size; + void (*drain_pebs)(struct pt_regs *regs); + struct event_constraint *pebs_constraints; + void (*pebs_aliases)(struct perf_event *event); +--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c ++++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c +@@ -241,7 +241,7 @@ static int alloc_pebs_buffer(int cpu) + if (!x86_pmu.pebs) + return 0; + +- buffer = kzalloc_node(PEBS_BUFFER_SIZE, GFP_KERNEL, node); ++ buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node); + if (unlikely(!buffer)) + return -ENOMEM; + +@@ -258,7 +258,7 @@ static int alloc_pebs_buffer(int cpu) + per_cpu(insn_buffer, cpu) = ibuffer; + } + +- max = PEBS_BUFFER_SIZE / x86_pmu.pebs_record_size; ++ max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size; + + ds->pebs_buffer_base = (u64)(unsigned long)buffer; + ds->pebs_index = ds->pebs_buffer_base; +@@ -1047,6 +1047,7 @@ void intel_ds_init(void) + + x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS); + x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS); ++ x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE; + if (x86_pmu.pebs) { + char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; + int format = x86_pmu.intel_cap.pebs_format; +@@ -1055,6 +1056,14 @@ void intel_ds_init(void) + case 0: + printk(KERN_CONT "PEBS fmt0%c, ", pebs_type); + x86_pmu.pebs_record_size = sizeof(struct pebs_record_core); ++ /* ++ * Using >PAGE_SIZE buffers makes the WRMSR to ++ * PERF_GLOBAL_CTRL in intel_pmu_enable_all() ++ * mysteriously hang on Core2. ++ * ++ * As a workaround, we don't do this. ++ */ ++ x86_pmu.pebs_buffer_size = PAGE_SIZE; + x86_pmu.drain_pebs = intel_pmu_drain_pebs_core; + break; + diff --git a/queue-3.14/0005-perf-x86-intel-Fix-PEBS-data-source-interpretation-o.patch b/queue-3.14/0005-perf-x86-intel-Fix-PEBS-data-source-interpretation-o.patch new file mode 100644 index 00000000000..fe3c4d13748 --- /dev/null +++ b/queue-3.14/0005-perf-x86-intel-Fix-PEBS-data-source-interpretation-o.patch @@ -0,0 +1,87 @@ +From 5e3f4cbd906c178510dccfed1131b007c96255ff Mon Sep 17 00:00:00 2001 +From: Andi Kleen +Date: Tue, 1 Mar 2016 14:25:24 -0800 +Subject: perf/x86/intel: Fix PEBS data source interpretation on Nehalem/Westmere + +From: Andi Kleen + +commit 5e3f4cbd906c178510dccfed1131b007c96255ff upstream. + +Jiri reported some time ago that some entries in the PEBS data source table +in perf do not agree with the SDM. We investigated and the bits +changed for Sandy Bridge, but the SDM was not updated. + +perf already implements the bits correctly for Sandy Bridge +and later. This patch patches it up for Nehalem and Westmere. + +Signed-off-by: Andi Kleen +Signed-off-by: Peter Zijlstra (Intel) +Cc: Linus Torvalds +Cc: Peter Zijlstra +Cc: Thomas Gleixner +Cc: jolsa@kernel.org +Link: http://lkml.kernel.org/r/1456871124-15985-1-git-send-email-andi@firstfloor.org +Signed-off-by: Ingo Molnar +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/perf_event.h | 2 ++ + arch/x86/kernel/cpu/perf_event_intel.c | 2 ++ + arch/x86/kernel/cpu/perf_event_intel_ds.c | 11 ++++++++++- + 3 files changed, 14 insertions(+), 1 deletion(-) + +--- a/arch/x86/kernel/cpu/perf_event.h ++++ b/arch/x86/kernel/cpu/perf_event.h +@@ -704,6 +704,8 @@ void intel_pmu_lbr_init_atom(void); + + void intel_pmu_lbr_init_snb(void); + ++void intel_pmu_pebs_data_source_nhm(void); ++ + int intel_pmu_setup_lbr_filter(struct perf_event *event); + + int p4_pmu_init(void); +--- a/arch/x86/kernel/cpu/perf_event_intel.c ++++ b/arch/x86/kernel/cpu/perf_event_intel.c +@@ -2411,6 +2411,7 @@ __init int intel_pmu_init(void) + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = + X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); + ++ intel_pmu_pebs_data_source_nhm(); + x86_add_quirk(intel_nehalem_quirk); + + pr_cont("Nehalem events, "); +@@ -2472,6 +2473,7 @@ __init int intel_pmu_init(void) + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = + X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1); + ++ intel_pmu_pebs_data_source_nhm(); + pr_cont("Westmere events, "); + break; + +--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c ++++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c +@@ -51,7 +51,8 @@ union intel_x86_pebs_dse { + #define OP_LH (P(OP, LOAD) | P(LVL, HIT)) + #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS)) + +-static const u64 pebs_data_source[] = { ++/* Version for Sandy Bridge and later */ ++static u64 pebs_data_source[] = { + P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),/* 0x00:ukn L3 */ + OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */ + OP_LH | P(LVL, LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */ +@@ -70,6 +71,14 @@ static const u64 pebs_data_source[] = { + OP_LH | P(LVL, UNC) | P(SNOOP, NONE), /* 0x0f: uncached */ + }; + ++/* Patch up minor differences in the bits */ ++void __init intel_pmu_pebs_data_source_nhm(void) ++{ ++ pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT); ++ pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); ++ pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM); ++} ++ + static u64 precise_store_data(u64 status) + { + union intel_x86_pebs_dse dse; diff --git a/queue-3.14/series b/queue-3.14/series index a580c6dfea2..1f88d131816 100644 --- a/queue-3.14/series +++ b/queue-3.14/series @@ -72,3 +72,5 @@ ocfs2-dlm-fix-race-between-convert-and-recovery.patch ocfs2-dlm-fix-bug-in-dlm_move_lockres_to_recovery_list.patch mtd-onenand-fix-deadlock-in-onenand_block_markbad.patch sched-cputime-fix-steal-time-accounting-vs.-cpu-hotplug.patch +0004-perf-x86-intel-Use-PAGE_SIZE-for-PEBS-buffer-size-on.patch +0005-perf-x86-intel-Fix-PEBS-data-source-interpretation-o.patch