From: Greg Kroah-Hartman Date: Tue, 17 Sep 2013 03:28:36 +0000 (-0700) Subject: 3.11-stable patches X-Git-Tag: v3.0.97~34 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d5d01d09e5a2bf1c940dad54923973d755ef4770;p=thirdparty%2Fkernel%2Fstable-queue.git 3.11-stable patches added patches: drm-i915-make-user-mode-sync-polarity-setting-explicit.patch --- diff --git a/queue-3.11/drm-i915-make-user-mode-sync-polarity-setting-explicit.patch b/queue-3.11/drm-i915-make-user-mode-sync-polarity-setting-explicit.patch new file mode 100644 index 00000000000..83ad21c277b --- /dev/null +++ b/queue-3.11/drm-i915-make-user-mode-sync-polarity-setting-explicit.patch @@ -0,0 +1,58 @@ +From 2960bc9cceecb5d556ce1c07656a6609e2f7e8b0 Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Tue, 30 Jul 2013 13:36:32 +0300 +Subject: drm/i915: make user mode sync polarity setting explicit + +From: Imre Deak + +commit 2960bc9cceecb5d556ce1c07656a6609e2f7e8b0 upstream. + +Userspace can pass a mode with an unspecified vsync/hsync polarity +setting. All encoders in the Intel driver take this to mean a negative +polarity setting. The HW readout/state checker code on the other hand +needs these flags to be explicitly set, otherwise the state checker will +WARN about the mismatch. + +Get rid of the WARN by making the polarity setting explicit in the +adjusted mode flags based on the requested mode flags. This will keep +the existing behavior otherwise. + +Note that we could guess from the other timing parameters whether the +user wanted a VESA or other standard mode and set the polarity +accordingly. This is what the NV driver does +(drivers/gpu/drm/nouveau/dispnv04/crtc.c), but I think that's not very +exact and would change the existing behavior of the Intel driver. + +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65442 +Signed-off-by: Imre Deak +Tested-by: cancan,feng +Reviewed-by: Chris Wilson +Signed-off-by: Daniel Vetter +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -7809,6 +7809,19 @@ intel_modeset_pipe_config(struct drm_crt + pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe; + pipe_config->shared_dpll = DPLL_ID_PRIVATE; + ++ /* ++ * Sanitize sync polarity flags based on requested ones. If neither ++ * positive or negative polarity is requested, treat this as meaning ++ * negative polarity. ++ */ ++ if (!(pipe_config->adjusted_mode.flags & ++ (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) ++ pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; ++ ++ if (!(pipe_config->adjusted_mode.flags & ++ (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) ++ pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; ++ + /* Compute a starting value for pipe_config->pipe_bpp taking the source + * plane pixel format and any sink constraints into account. Returns the + * source plane bpp so that dithering can be selected on mismatches diff --git a/queue-3.11/series b/queue-3.11/series index c17b9ec7b18..5c2d2ba1ac8 100644 --- a/queue-3.11/series +++ b/queue-3.11/series @@ -2,3 +2,4 @@ arc-smp-failed-to-boot-due-to-missing-ivt-setup.patch ipc-msg.c-fix-lost-wakeup-in-msgsnd.patch xtensa-fix-broken-allmodconfig-build.patch scsi-allow-mpt-fusion-sas-3.0-driver-to-be-built-into-the-kernel.patch +drm-i915-make-user-mode-sync-polarity-setting-explicit.patch