From: Dmitry Osipenko Date: Tue, 3 Oct 2017 23:02:41 +0000 (+0300) Subject: clk: tegra: Bump SCLK clock rate to 216 MHz X-Git-Tag: v4.15-rc1~48^2~16^2~3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d80a32fe98b7ce428669b774c3d10ecae3bc6e6d;p=thirdparty%2Fkernel%2Flinux.git clk: tegra: Bump SCLK clock rate to 216 MHz AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Thierry Reding --- diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 57a1387ea9921..cbd5a2e5c569b 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1020,7 +1020,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 }, { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 }, { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 },