From: Michael Clark <mjc@sifive.com>
Date: Sat, 16 Mar 2019 01:21:21 +0000 (+0000)
Subject: RISC-V: Update load reservation comment in do_interrupt
X-Git-Tag: v4.0.0-rc0~3^2~4
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=d9360e96885dbd69ce4aa925d1701c7a10cf54ae;p=thirdparty%2Fqemu.git

RISC-V: Update load reservation comment in do_interrupt

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 6d3fbc34016..b17f169681a 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -525,7 +525,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
             ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);
         riscv_cpu_set_mode(env, PRV_M);
     }
-    /* TODO yield load reservation  */
+
+    /* NOTE: it is not necessary to yield load reservations here. It is only
+     * necessary for an SC from "another hart" to cause a load reservation
+     * to be yielded. Refer to the memory consistency model section of the
+     * RISC-V ISA Specification.
+     */
+
 #endif
     cs->exception_index = EXCP_NONE; /* mark handled to qemu */
 }