From: Anton Blanchard Date: Tue, 4 Jun 2019 19:01:13 +0000 (+0100) Subject: target/ppc: Fix xxbrq, xxbrw X-Git-Tag: v4.0.1~78 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=da3bd13802dd49052dc1ac6443e24635dbf2ee51;p=thirdparty%2Fqemu.git target/ppc: Fix xxbrq, xxbrw Fix a typo in xxbrq and xxbrw where we put both results into the lower doubleword. Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") Signed-off-by: Anton Blanchard Message-Id: <20190507004811.29968-3-anton@ozlabs.org> Signed-off-by: David Gibson (upstream commit d47a751adab7833e9831408376077bc8dba41d5d) Acked-by: David Gibson Signed-off-by: Michael Roth --- diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 96e4ff4411f..7778d5d6514 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1192,7 +1192,7 @@ static void gen_xxbrq(DisasContext *ctx) tcg_gen_bswap64_i64(xtl, xbh); set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_gen_mov_i64(xth, t0); - set_cpu_vsrl(xT(ctx->opcode), xth); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_temp_free_i64(t0); tcg_temp_free_i64(xth); @@ -1220,7 +1220,7 @@ static void gen_xxbrw(DisasContext *ctx) get_cpu_vsrl(xbl, xB(ctx->opcode)); gen_bswap32x4(xth, xtl, xbh, xbl); - set_cpu_vsrl(xT(ctx->opcode), xth); + set_cpu_vsrh(xT(ctx->opcode), xth); set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free_i64(xth);