From: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Date: Thu, 11 Mar 2021 10:30:36 +0000 (+0100)
Subject: target/riscv: Use background registers also for MSTATUS_MPV
X-Git-Tag: v6.0.0-rc0~7^2~8
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=db9ab38b81058b41e5f469165067feea46762eee;p=thirdparty%2Fqemu.git

target/riscv: Use background registers also for MSTATUS_MPV

The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b15a60d8a2d..8d4a62988dc 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -364,7 +364,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
      * was called. Background registers will be used if the guest has
      * forced a two stage translation to be on (in HS or M mode).
      */
-    if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
+    if (!riscv_cpu_virt_enabled(env) && two_stage) {
         use_background = true;
     }