From: Greg Kroah-Hartman Date: Sun, 27 Aug 2023 07:02:05 +0000 (+0200) Subject: 4.19-stable patches X-Git-Tag: v6.1.49~37 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=dc43e5aa1d8018534c9ed344abcf7f2ab139cbaf;p=thirdparty%2Fkernel%2Fstable-queue.git 4.19-stable patches added patches: x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch --- diff --git a/queue-4.19/series b/queue-4.19/series index d97039c4990..d680230fa39 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -127,3 +127,4 @@ batman-adv-fix-batadv_v_ogm_aggr_send-memory-leak.patch lib-clz_ctz.c-fix-__clzdi2-and-__ctzdi2-for-32-bit-kernels.patch media-vcodec-fix-potential-array-out-of-bounds-in-encoder-queue_setup.patch pci-acpiphp-use-pci_assign_unassigned_bridge_resources-only-for-non-root-bus.patch +x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch diff --git a/queue-4.19/x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch b/queue-4.19/x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch new file mode 100644 index 00000000000..8c2bed18ba8 --- /dev/null +++ b/queue-4.19/x86-fpu-set-x86_feature_osxsave-feature-after-enabling-osxsave-in-cr4.patch @@ -0,0 +1,62 @@ +From 2c66ca3949dc701da7f4c9407f2140ae425683a5 Mon Sep 17 00:00:00 2001 +From: Feng Tang +Date: Wed, 23 Aug 2023 14:57:47 +0800 +Subject: x86/fpu: Set X86_FEATURE_OSXSAVE feature after enabling OSXSAVE in CR4 + +From: Feng Tang + +commit 2c66ca3949dc701da7f4c9407f2140ae425683a5 upstream. + +0-Day found a 34.6% regression in stress-ng's 'af-alg' test case, and +bisected it to commit b81fac906a8f ("x86/fpu: Move FPU initialization into +arch_cpu_finalize_init()"), which optimizes the FPU init order, and moves +the CR4_OSXSAVE enabling into a later place: + + arch_cpu_finalize_init + identify_boot_cpu + identify_cpu + generic_identify + get_cpu_cap --> setup cpu capability + ... + fpu__init_cpu + fpu__init_cpu_xstate + cr4_set_bits(X86_CR4_OSXSAVE); + +As the FPU is not yet initialized the CPU capability setup fails to set +X86_FEATURE_OSXSAVE. Many security module like 'camellia_aesni_avx_x86_64' +depend on this feature and therefore fail to load, causing the regression. + +Cure this by setting X86_FEATURE_OSXSAVE feature right after OSXSAVE +enabling. + +[ tglx: Moved it into the actual BSP FPU initialization code and added a comment ] + +Fixes: b81fac906a8f ("x86/fpu: Move FPU initialization into arch_cpu_finalize_init()") +Reported-by: kernel test robot +Signed-off-by: Feng Tang +Signed-off-by: Thomas Gleixner +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/lkml/202307192135.203ac24e-oliver.sang@intel.com +Link: https://lore.kernel.org/lkml/20230823065747.92257-1-feng.tang@intel.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/fpu/xstate.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/x86/kernel/fpu/xstate.c ++++ b/arch/x86/kernel/fpu/xstate.c +@@ -811,6 +811,14 @@ void __init fpu__init_system_xstate(void + fpu__init_prepare_fx_sw_frame(); + setup_init_fpu_buf(); + setup_xstate_comp(); ++ ++ /* ++ * CPU capabilities initialization runs before FPU init. So ++ * X86_FEATURE_OSXSAVE is not set. Now that XSAVE is completely ++ * functional, set the feature bit so depending code works. ++ */ ++ setup_force_cpu_cap(X86_FEATURE_OSXSAVE); ++ + print_xstate_offset_size(); + + pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n",