From: Greg Kroah-Hartman Date: Fri, 27 Sep 2013 22:26:23 +0000 (-0700) Subject: 3.0-stable patches X-Git-Tag: v3.0.98~22 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=dc97fc904287fd144b268e4d9f310ab61e2abdfc;p=thirdparty%2Fkernel%2Fstable-queue.git 3.0-stable patches added patches: drm-radeon-fix-handling-of-variable-sized-arrays-for-router-objects.patch drm-radeon-fix-resume-on-some-rs4xx-boards-v2.patch drm-radeon-update-line-buffer-allocation-for-dce4.1-5.patch --- diff --git a/queue-3.0/drm-radeon-fix-handling-of-variable-sized-arrays-for-router-objects.patch b/queue-3.0/drm-radeon-fix-handling-of-variable-sized-arrays-for-router-objects.patch new file mode 100644 index 00000000000..54eef08d6e0 --- /dev/null +++ b/queue-3.0/drm-radeon-fix-handling-of-variable-sized-arrays-for-router-objects.patch @@ -0,0 +1,52 @@ +From fb93df1c2d8b3b1fb16d6ee9e32554e0c038815d Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Tue, 27 Aug 2013 12:36:01 -0400 +Subject: drm/radeon: fix handling of variable sized arrays for router objects + +From: Alex Deucher + +commit fb93df1c2d8b3b1fb16d6ee9e32554e0c038815d upstream. + +The table has the following format: + +typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure +{ + UCHAR ucNumberOfSrc; + USHORT usSrcObjectID[1]; + UCHAR ucNumberOfDst; + USHORT usDstObjectID[1]; +}ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; + +usSrcObjectID[] and usDstObjectID[] are variably sized, so we +can't access them directly. Use pointers and update the offset +appropriately when accessing the Dst members. + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_atombios.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_atombios.c ++++ b/drivers/gpu/drm/radeon/radeon_atombios.c +@@ -751,13 +751,16 @@ bool radeon_get_atom_connector_info_from + (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) + (ctx->bios + data_offset + + le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); ++ u8 *num_dst_objs = (u8 *) ++ ((u8 *)router_src_dst_table + 1 + ++ (router_src_dst_table->ucNumberOfSrc * 2)); ++ u16 *dst_objs = (u16 *)(num_dst_objs + 1); + int enum_id; + + router.router_id = router_obj_id; +- for (enum_id = 0; enum_id < router_src_dst_table->ucNumberOfDst; +- enum_id++) { ++ for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { + if (le16_to_cpu(path->usConnObjectId) == +- le16_to_cpu(router_src_dst_table->usDstObjectID[enum_id])) ++ le16_to_cpu(dst_objs[enum_id])) + break; + } + diff --git a/queue-3.0/drm-radeon-fix-resume-on-some-rs4xx-boards-v2.patch b/queue-3.0/drm-radeon-fix-resume-on-some-rs4xx-boards-v2.patch new file mode 100644 index 00000000000..acd25b2838a --- /dev/null +++ b/queue-3.0/drm-radeon-fix-resume-on-some-rs4xx-boards-v2.patch @@ -0,0 +1,48 @@ +From acf88deb8ddbb73acd1c3fa32fde51af9153227f Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 26 Aug 2013 17:52:12 -0400 +Subject: drm/radeon: fix resume on some rs4xx boards (v2) + +From: Alex Deucher + +commit acf88deb8ddbb73acd1c3fa32fde51af9153227f upstream. + +Setting MC_MISC_CNTL.GART_INDEX_REG_EN causes hangs on +some boards on resume. The systems seem to work fine +without touching this bit so leave it as is. + +v2: read-modify-write the GART_INDEX_REG_EN bit. +I suspect the problem is that we are losing the other +settings in the register. + +fixes: +https://bugs.freedesktop.org/show_bug.cgi?id=52952 + +Reported-by: Ondrej Zary +Tested-by: Daniel Tobias +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/rs400.c | 9 ++++++--- + 1 file changed, 6 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/radeon/rs400.c ++++ b/drivers/gpu/drm/radeon/rs400.c +@@ -174,10 +174,13 @@ int rs400_gart_enable(struct radeon_devi + /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, + * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ + if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { +- WREG32_MC(RS480_MC_MISC_CNTL, +- (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); ++ tmp = RREG32_MC(RS480_MC_MISC_CNTL); ++ tmp |= RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN; ++ WREG32_MC(RS480_MC_MISC_CNTL, tmp); + } else { +- WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); ++ tmp = RREG32_MC(RS480_MC_MISC_CNTL); ++ tmp |= RS480_GART_INDEX_REG_EN; ++ WREG32_MC(RS480_MC_MISC_CNTL, tmp); + } + /* Enable gart */ + WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); diff --git a/queue-3.0/drm-radeon-update-line-buffer-allocation-for-dce4.1-5.patch b/queue-3.0/drm-radeon-update-line-buffer-allocation-for-dce4.1-5.patch new file mode 100644 index 00000000000..6162c21b6d7 --- /dev/null +++ b/queue-3.0/drm-radeon-update-line-buffer-allocation-for-dce4.1-5.patch @@ -0,0 +1,88 @@ +From 0b31e02363b0db4e7931561bc6c141436e729d9f Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 19 Aug 2013 11:06:50 -0400 +Subject: drm/radeon: update line buffer allocation for dce4.1/5 + +From: Alex Deucher + +commit 0b31e02363b0db4e7931561bc6c141436e729d9f upstream. + +We need to allocate line buffer to each display when +setting up the watermarks. Failure to do so can lead +to a blank screen. This fixes blank screen problems +on dce4.1/5 asics. + +Based on an initial fix from: +Jay Cornwall + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/evergreen.c | 25 +++++++++++++++++++++---- + drivers/gpu/drm/radeon/evergreend.h | 4 ++++ + 2 files changed, 25 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen.c ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -419,7 +419,8 @@ static u32 evergreen_line_buffer_adjust( + struct drm_display_mode *mode, + struct drm_display_mode *other_mode) + { +- u32 tmp; ++ u32 tmp, buffer_alloc, i; ++ u32 pipe_offset = radeon_crtc->crtc_id * 0x20; + /* + * Line Buffer Setup + * There are 3 line buffers, each one shared by 2 display controllers. +@@ -442,18 +443,34 @@ static u32 evergreen_line_buffer_adjust( + * non-linked crtcs for maximum line buffer allocation. + */ + if (radeon_crtc->base.enabled && mode) { +- if (other_mode) ++ if (other_mode) { + tmp = 0; /* 1/2 */ +- else ++ buffer_alloc = 1; ++ } else { + tmp = 2; /* whole */ +- } else ++ buffer_alloc = 2; ++ } ++ } else { + tmp = 0; ++ buffer_alloc = 0; ++ } + + /* second controller of the pair uses second half of the lb */ + if (radeon_crtc->crtc_id % 2) + tmp += 4; + WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); + ++ if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { ++ WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, ++ DMIF_BUFFERS_ALLOCATED(buffer_alloc)); ++ for (i = 0; i < rdev->usec_timeout; i++) { ++ if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & ++ DMIF_BUFFERS_ALLOCATED_COMPLETED) ++ break; ++ udelay(1); ++ } ++ } ++ + if (radeon_crtc->base.enabled && mode) { + switch (tmp) { + case 0: +--- a/drivers/gpu/drm/radeon/evergreend.h ++++ b/drivers/gpu/drm/radeon/evergreend.h +@@ -450,6 +450,10 @@ + # define LATENCY_LOW_WATERMARK(x) ((x) << 0) + # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) + ++#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 ++# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) ++# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) ++ + #define IH_RB_CNTL 0x3e00 + # define IH_RB_ENABLE (1 << 0) + # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ diff --git a/queue-3.0/series b/queue-3.0/series index 31a749c367e..e249b3f1783 100644 --- a/queue-3.0/series +++ b/queue-3.0/series @@ -4,3 +4,6 @@ rt2800-fix-wrong-tx-power-compensation.patch hid-provide-a-helper-for-validating-hid-reports.patch hid-zeroplus-validate-output-report-details.patch drm-radeon-fix-lcd-record-parsing.patch +drm-radeon-update-line-buffer-allocation-for-dce4.1-5.patch +drm-radeon-fix-resume-on-some-rs4xx-boards-v2.patch +drm-radeon-fix-handling-of-variable-sized-arrays-for-router-objects.patch