From: Greg Kroah-Hartman Date: Fri, 10 Apr 2015 13:12:35 +0000 (+0200) Subject: 3.19-stable patches X-Git-Tag: v3.10.74~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=dd5db227559bb6d0b94273c65e55c05211900e2a;p=thirdparty%2Fkernel%2Fstable-queue.git 3.19-stable patches added patches: arm64-percpu-make-this_cpu-accessors-pre-empt-safe.patch arm64-use-the-reserved-ttbr0-if-context-switching-to-the-init_mm.patch mfd-kempld-core-fix-callback-return-value-check.patch net-ethernet-pcnet32-setup-the-sram-and-nouflo-on-am79c97-3-5.patch powerpc-book3s-fix-the-mce-code-to-use-config_kvm_book3s_64_handler.patch powerpc-mpc85xx-add-ranges-to-etsec2-nodes.patch powerpc-pseries-little-endian-fixes-for-post-mobility-device-tree-update.patch regulator-palmas-correct-tps659038-register-definition-for-regen2.patch --- diff --git a/queue-3.19/arm64-percpu-make-this_cpu-accessors-pre-empt-safe.patch b/queue-3.19/arm64-percpu-make-this_cpu-accessors-pre-empt-safe.patch new file mode 100644 index 00000000000..dc67acb4281 --- /dev/null +++ b/queue-3.19/arm64-percpu-make-this_cpu-accessors-pre-empt-safe.patch @@ -0,0 +1,137 @@ +From f3eab7184ddcd4867cf42e3274ba24a66e1e093d Mon Sep 17 00:00:00 2001 +From: Steve Capper +Date: Sun, 22 Mar 2015 14:51:51 +0000 +Subject: arm64: percpu: Make this_cpu accessors pre-empt safe + +From: Steve Capper + +commit f3eab7184ddcd4867cf42e3274ba24a66e1e093d upstream. + +this_cpu operations were implemented for arm64 in: + 5284e1b arm64: xchg: Implement cmpxchg_double + f97fc81 arm64: percpu: Implement this_cpu operations + +Unfortunately, it is possible for pre-emption to take place between +address generation and data access. This can lead to cases where data +is being manipulated by this_cpu for a different CPU than it was +called on. Which effectively breaks the spec. + +This patch disables pre-emption for the this_cpu operations +guaranteeing that address generation and data manipulation take place +without a pre-emption in-between. + +Fixes: 5284e1b4bc8a ("arm64: xchg: Implement cmpxchg_double") +Fixes: f97fc810798c ("arm64: percpu: Implement this_cpu operations") +Reported-by: Mark Rutland +Acked-by: Will Deacon +Signed-off-by: Steve Capper +[catalin.marinas@arm.com: remove space after type cast] +Signed-off-by: Catalin Marinas +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/include/asm/cmpxchg.h | 30 ++++++++++++++++++++------ + arch/arm64/include/asm/percpu.h | 44 +++++++++++++++++++++++++++++---------- + 2 files changed, 56 insertions(+), 18 deletions(-) + +--- a/arch/arm64/include/asm/cmpxchg.h ++++ b/arch/arm64/include/asm/cmpxchg.h +@@ -246,14 +246,30 @@ static inline unsigned long __cmpxchg_mb + __ret; \ + }) + +-#define this_cpu_cmpxchg_1(ptr, o, n) cmpxchg_local(raw_cpu_ptr(&(ptr)), o, n) +-#define this_cpu_cmpxchg_2(ptr, o, n) cmpxchg_local(raw_cpu_ptr(&(ptr)), o, n) +-#define this_cpu_cmpxchg_4(ptr, o, n) cmpxchg_local(raw_cpu_ptr(&(ptr)), o, n) +-#define this_cpu_cmpxchg_8(ptr, o, n) cmpxchg_local(raw_cpu_ptr(&(ptr)), o, n) ++#define _protect_cmpxchg_local(pcp, o, n) \ ++({ \ ++ typeof(*raw_cpu_ptr(&(pcp))) __ret; \ ++ preempt_disable(); \ ++ __ret = cmpxchg_local(raw_cpu_ptr(&(pcp)), o, n); \ ++ preempt_enable(); \ ++ __ret; \ ++}) ++ ++#define this_cpu_cmpxchg_1(ptr, o, n) _protect_cmpxchg_local(ptr, o, n) ++#define this_cpu_cmpxchg_2(ptr, o, n) _protect_cmpxchg_local(ptr, o, n) ++#define this_cpu_cmpxchg_4(ptr, o, n) _protect_cmpxchg_local(ptr, o, n) ++#define this_cpu_cmpxchg_8(ptr, o, n) _protect_cmpxchg_local(ptr, o, n) + +-#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \ +- cmpxchg_double_local(raw_cpu_ptr(&(ptr1)), raw_cpu_ptr(&(ptr2)), \ +- o1, o2, n1, n2) ++#define this_cpu_cmpxchg_double_8(ptr1, ptr2, o1, o2, n1, n2) \ ++({ \ ++ int __ret; \ ++ preempt_disable(); \ ++ __ret = cmpxchg_double_local( raw_cpu_ptr(&(ptr1)), \ ++ raw_cpu_ptr(&(ptr2)), \ ++ o1, o2, n1, n2); \ ++ preempt_enable(); \ ++ __ret; \ ++}) + + #define cmpxchg64(ptr,o,n) cmpxchg((ptr),(o),(n)) + #define cmpxchg64_local(ptr,o,n) cmpxchg_local((ptr),(o),(n)) +--- a/arch/arm64/include/asm/percpu.h ++++ b/arch/arm64/include/asm/percpu.h +@@ -204,25 +204,47 @@ static inline unsigned long __percpu_xch + return ret; + } + ++#define _percpu_read(pcp) \ ++({ \ ++ typeof(pcp) __retval; \ ++ preempt_disable(); \ ++ __retval = (typeof(pcp))__percpu_read(raw_cpu_ptr(&(pcp)), \ ++ sizeof(pcp)); \ ++ preempt_enable(); \ ++ __retval; \ ++}) ++ ++#define _percpu_write(pcp, val) \ ++do { \ ++ preempt_disable(); \ ++ __percpu_write(raw_cpu_ptr(&(pcp)), (unsigned long)(val), \ ++ sizeof(pcp)); \ ++ preempt_enable(); \ ++} while(0) \ ++ ++#define _pcp_protect(operation, pcp, val) \ ++({ \ ++ typeof(pcp) __retval; \ ++ preempt_disable(); \ ++ __retval = (typeof(pcp))operation(raw_cpu_ptr(&(pcp)), \ ++ (val), sizeof(pcp)); \ ++ preempt_enable(); \ ++ __retval; \ ++}) ++ + #define _percpu_add(pcp, val) \ +- __percpu_add(raw_cpu_ptr(&(pcp)), val, sizeof(pcp)) ++ _pcp_protect(__percpu_add, pcp, val) + +-#define _percpu_add_return(pcp, val) (typeof(pcp)) (_percpu_add(pcp, val)) ++#define _percpu_add_return(pcp, val) _percpu_add(pcp, val) + + #define _percpu_and(pcp, val) \ +- __percpu_and(raw_cpu_ptr(&(pcp)), val, sizeof(pcp)) ++ _pcp_protect(__percpu_and, pcp, val) + + #define _percpu_or(pcp, val) \ +- __percpu_or(raw_cpu_ptr(&(pcp)), val, sizeof(pcp)) +- +-#define _percpu_read(pcp) (typeof(pcp)) \ +- (__percpu_read(raw_cpu_ptr(&(pcp)), sizeof(pcp))) +- +-#define _percpu_write(pcp, val) \ +- __percpu_write(raw_cpu_ptr(&(pcp)), (unsigned long)(val), sizeof(pcp)) ++ _pcp_protect(__percpu_or, pcp, val) + + #define _percpu_xchg(pcp, val) (typeof(pcp)) \ +- (__percpu_xchg(raw_cpu_ptr(&(pcp)), (unsigned long)(val), sizeof(pcp))) ++ _pcp_protect(__percpu_xchg, pcp, (unsigned long)(val)) + + #define this_cpu_add_1(pcp, val) _percpu_add(pcp, val) + #define this_cpu_add_2(pcp, val) _percpu_add(pcp, val) diff --git a/queue-3.19/arm64-use-the-reserved-ttbr0-if-context-switching-to-the-init_mm.patch b/queue-3.19/arm64-use-the-reserved-ttbr0-if-context-switching-to-the-init_mm.patch new file mode 100644 index 00000000000..cb550cb32e3 --- /dev/null +++ b/queue-3.19/arm64-use-the-reserved-ttbr0-if-context-switching-to-the-init_mm.patch @@ -0,0 +1,40 @@ +From e53f21bce4d35a93b23d8fa1a840860f6c74f59e Mon Sep 17 00:00:00 2001 +From: Catalin Marinas +Date: Mon, 23 Mar 2015 15:06:50 +0000 +Subject: arm64: Use the reserved TTBR0 if context switching to the init_mm + +From: Catalin Marinas + +commit e53f21bce4d35a93b23d8fa1a840860f6c74f59e upstream. + +The idle_task_exit() function may call switch_mm() with next == +&init_mm. On arm64, init_mm.pgd cannot be used for user mappings, so +this patch simply sets the reserved TTBR0. + +Reported-by: Jon Medhurst (Tixy) +Tested-by: Jon Medhurst (Tixy) +Signed-off-by: Catalin Marinas +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/include/asm/mmu_context.h | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/arch/arm64/include/asm/mmu_context.h ++++ b/arch/arm64/include/asm/mmu_context.h +@@ -151,6 +151,15 @@ switch_mm(struct mm_struct *prev, struct + { + unsigned int cpu = smp_processor_id(); + ++ /* ++ * init_mm.pgd does not contain any user mappings and it is always ++ * active for kernel addresses in TTBR1. Just set the reserved TTBR0. ++ */ ++ if (next == &init_mm) { ++ cpu_set_reserved_ttbr0(); ++ return; ++ } ++ + if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) + check_and_switch_context(next, tsk); + } diff --git a/queue-3.19/mfd-kempld-core-fix-callback-return-value-check.patch b/queue-3.19/mfd-kempld-core-fix-callback-return-value-check.patch new file mode 100644 index 00000000000..188c9d68e5a --- /dev/null +++ b/queue-3.19/mfd-kempld-core-fix-callback-return-value-check.patch @@ -0,0 +1,31 @@ +From c8648508ebfc597058d2cd00b6c539110264a167 Mon Sep 17 00:00:00 2001 +From: Ameya Palande <2ameya@gmail.com> +Date: Thu, 26 Feb 2015 12:05:51 -0800 +Subject: mfd: kempld-core: Fix callback return value check + +From: Ameya Palande <2ameya@gmail.com> + +commit c8648508ebfc597058d2cd00b6c539110264a167 upstream. + +On success, callback function returns 0. So invert the if condition +check so that we can break out of loop. + +Signed-off-by: Ameya Palande <2ameya@gmail.com> +Signed-off-by: Lee Jones +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mfd/kempld-core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mfd/kempld-core.c ++++ b/drivers/mfd/kempld-core.c +@@ -739,7 +739,7 @@ static int __init kempld_init(void) + for (id = kempld_dmi_table; + id->matches[0].slot != DMI_NONE; id++) + if (strstr(id->ident, force_device_id)) +- if (id->callback && id->callback(id)) ++ if (id->callback && !id->callback(id)) + break; + if (id->matches[0].slot == DMI_NONE) + return -ENODEV; diff --git a/queue-3.19/net-ethernet-pcnet32-setup-the-sram-and-nouflo-on-am79c97-3-5.patch b/queue-3.19/net-ethernet-pcnet32-setup-the-sram-and-nouflo-on-am79c97-3-5.patch new file mode 100644 index 00000000000..930d389eb64 --- /dev/null +++ b/queue-3.19/net-ethernet-pcnet32-setup-the-sram-and-nouflo-on-am79c97-3-5.patch @@ -0,0 +1,96 @@ +From 87f966d97b89774162df04d2106c6350c8fe4cb3 Mon Sep 17 00:00:00 2001 +From: Markos Chandras +Date: Thu, 19 Mar 2015 10:28:14 +0000 +Subject: net: ethernet: pcnet32: Setup the SRAM and NOUFLO on Am79C97{3, 5} + +From: Markos Chandras + +commit 87f966d97b89774162df04d2106c6350c8fe4cb3 upstream. + +On a MIPS Malta board, tons of fifo underflow errors have been observed +when using u-boot as bootloader instead of YAMON. The reason for that +is that YAMON used to set the pcnet device to SRAM mode but u-boot does +not. As a result, the default Tx threshold (64 bytes) is now too small to +keep the fifo relatively used and it can result to Tx fifo underflow errors. +As a result of which, it's best to setup the SRAM on supported controllers +so we can always use the NOUFLO bit. + +Cc: +Cc: +Cc: Don Fry +Signed-off-by: Markos Chandras +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/net/ethernet/amd/pcnet32.c | 31 +++++++++++++++++++++++++++++-- + 1 file changed, 29 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/amd/pcnet32.c ++++ b/drivers/net/ethernet/amd/pcnet32.c +@@ -1543,7 +1543,7 @@ pcnet32_probe1(unsigned long ioaddr, int + { + struct pcnet32_private *lp; + int i, media; +- int fdx, mii, fset, dxsuflo; ++ int fdx, mii, fset, dxsuflo, sram; + int chip_version; + char *chipname; + struct net_device *dev; +@@ -1580,7 +1580,7 @@ pcnet32_probe1(unsigned long ioaddr, int + } + + /* initialize variables */ +- fdx = mii = fset = dxsuflo = 0; ++ fdx = mii = fset = dxsuflo = sram = 0; + chip_version = (chip_version >> 12) & 0xffff; + + switch (chip_version) { +@@ -1613,6 +1613,7 @@ pcnet32_probe1(unsigned long ioaddr, int + chipname = "PCnet/FAST III 79C973"; /* PCI */ + fdx = 1; + mii = 1; ++ sram = 1; + break; + case 0x2626: + chipname = "PCnet/Home 79C978"; /* PCI */ +@@ -1636,6 +1637,7 @@ pcnet32_probe1(unsigned long ioaddr, int + chipname = "PCnet/FAST III 79C975"; /* PCI */ + fdx = 1; + mii = 1; ++ sram = 1; + break; + case 0x2628: + chipname = "PCnet/PRO 79C976"; +@@ -1664,6 +1666,31 @@ pcnet32_probe1(unsigned long ioaddr, int + dxsuflo = 1; + } + ++ /* ++ * The Am79C973/Am79C975 controllers come with 12K of SRAM ++ * which we can use for the Tx/Rx buffers but most importantly, ++ * the use of SRAM allow us to use the BCR18:NOUFLO bit to avoid ++ * Tx fifo underflows. ++ */ ++ if (sram) { ++ /* ++ * The SRAM is being configured in two steps. First we ++ * set the SRAM size in the BCR25:SRAM_SIZE bits. According ++ * to the datasheet, each bit corresponds to a 512-byte ++ * page so we can have at most 24 pages. The SRAM_SIZE ++ * holds the value of the upper 8 bits of the 16-bit SRAM size. ++ * The low 8-bits start at 0x00 and end at 0xff. So the ++ * address range is from 0x0000 up to 0x17ff. Therefore, ++ * the SRAM_SIZE is set to 0x17. The next step is to set ++ * the BCR26:SRAM_BND midway through so the Tx and Rx ++ * buffers can share the SRAM equally. ++ */ ++ a->write_bcr(ioaddr, 25, 0x17); ++ a->write_bcr(ioaddr, 26, 0xc); ++ /* And finally enable the NOUFLO bit */ ++ a->write_bcr(ioaddr, 18, a->read_bcr(ioaddr, 18) | (1 << 11)); ++ } ++ + dev = alloc_etherdev(sizeof(*lp)); + if (!dev) { + ret = -ENOMEM; diff --git a/queue-3.19/powerpc-book3s-fix-the-mce-code-to-use-config_kvm_book3s_64_handler.patch b/queue-3.19/powerpc-book3s-fix-the-mce-code-to-use-config_kvm_book3s_64_handler.patch new file mode 100644 index 00000000000..93ce519947c --- /dev/null +++ b/queue-3.19/powerpc-book3s-fix-the-mce-code-to-use-config_kvm_book3s_64_handler.patch @@ -0,0 +1,40 @@ +From 44d5f6f5901e996744858c175baee320ccf1eda3 Mon Sep 17 00:00:00 2001 +From: Mahesh Salgaonkar +Date: Tue, 17 Mar 2015 16:14:41 +0530 +Subject: powerpc/book3s: Fix the MCE code to use CONFIG_KVM_BOOK3S_64_HANDLER + +From: Mahesh Salgaonkar + +commit 44d5f6f5901e996744858c175baee320ccf1eda3 upstream. + +commit id 2ba9f0d has changed CONFIG_KVM_BOOK3S_64_HV to tristate to allow +HV/PR bits to be built as modules. But the MCE code still depends on +CONFIG_KVM_BOOK3S_64_HV which is wrong. When user selects +CONFIG_KVM_BOOK3S_64_HV=m to build HV/PR bits as a separate module the +relevant MCE code gets excluded. + +This patch fixes the MCE code to use CONFIG_KVM_BOOK3S_64_HANDLER. This +makes sure that the relevant MCE code is included when HV/PR bits +are built as a separate modules. + +Fixes: 2ba9f0d88750 ("kvm: powerpc: book3s: Support building HV and PR KVM as module") +Signed-off-by: Mahesh Salgaonkar +Acked-by: Paul Mackerras +Signed-off-by: Michael Ellerman +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/kernel/exceptions-64s.S | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/powerpc/kernel/exceptions-64s.S ++++ b/arch/powerpc/kernel/exceptions-64s.S +@@ -1408,7 +1408,7 @@ machine_check_handle_early: + bne 9f /* continue in V mode if we are. */ + + 5: +-#ifdef CONFIG_KVM_BOOK3S_64_HV ++#ifdef CONFIG_KVM_BOOK3S_64_HANDLER + /* + * We are coming from kernel context. Check if we are coming from + * guest. if yes, then we can continue. We will fall through diff --git a/queue-3.19/powerpc-mpc85xx-add-ranges-to-etsec2-nodes.patch b/queue-3.19/powerpc-mpc85xx-add-ranges-to-etsec2-nodes.patch new file mode 100644 index 00000000000..ad46810d71d --- /dev/null +++ b/queue-3.19/powerpc-mpc85xx-add-ranges-to-etsec2-nodes.patch @@ -0,0 +1,55 @@ +From bb344ca5b90df62b1a3b7a35c6a9d00b306a170d Mon Sep 17 00:00:00 2001 +From: Scott Wood +Date: Wed, 17 Dec 2014 19:06:31 -0600 +Subject: powerpc/mpc85xx: Add ranges to etsec2 nodes + +From: Scott Wood + +commit bb344ca5b90df62b1a3b7a35c6a9d00b306a170d upstream. + +Commit 746c9e9f92dd "of/base: Fix PowerPC address parsing hack" limited +the applicability of the workaround whereby a missing ranges is treated +as an empty ranges. This workaround was hiding a bug in the etsec2 +device tree nodes, which have children with reg, but did not have +ranges. + +Signed-off-by: Scott Wood +Reported-by: Alexander Graf +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi | 1 + + arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi | 1 + + arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi | 1 + + 3 files changed, 3 insertions(+) + +--- a/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi ++++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-0.dtsi +@@ -50,6 +50,7 @@ ethernet@b0000 { + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; ++ ranges; + + queue-group@b0000 { + #address-cells = <1>; +--- a/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi ++++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-1.dtsi +@@ -50,6 +50,7 @@ ethernet@b1000 { + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; ++ ranges; + + queue-group@b1000 { + #address-cells = <1>; +--- a/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi ++++ b/arch/powerpc/boot/dts/fsl/pq3-etsec2-2.dtsi +@@ -49,6 +49,7 @@ ethernet@b2000 { + fsl,num_tx_queues = <0x8>; + fsl,magic-packet; + local-mac-address = [ 00 00 00 00 00 00 ]; ++ ranges; + + queue-group@b2000 { + #address-cells = <1>; diff --git a/queue-3.19/powerpc-pseries-little-endian-fixes-for-post-mobility-device-tree-update.patch b/queue-3.19/powerpc-pseries-little-endian-fixes-for-post-mobility-device-tree-update.patch new file mode 100644 index 00000000000..598a647321b --- /dev/null +++ b/queue-3.19/powerpc-pseries-little-endian-fixes-for-post-mobility-device-tree-update.patch @@ -0,0 +1,165 @@ +From f6ff04149637723261aa4738958b0098b929ee9e Mon Sep 17 00:00:00 2001 +From: Tyrel Datwyler +Date: Wed, 4 Mar 2015 11:59:33 -0800 +Subject: powerpc/pseries: Little endian fixes for post mobility device tree update + +From: Tyrel Datwyler + +commit f6ff04149637723261aa4738958b0098b929ee9e upstream. + +We currently use the device tree update code in the kernel after resuming +from a suspend operation to re-sync the kernels view of the device tree with +that of the hypervisor. The code as it stands is not endian safe as it relies +on parsing buffers returned by RTAS calls that thusly contains data in big +endian format. + +This patch annotates variables and structure members with __be types as well +as performing necessary byte swaps to cpu endian for data that needs to be +parsed. + +Signed-off-by: Tyrel Datwyler +Cc: Nathan Fontenot +Cc: Cyril Bur +Signed-off-by: Michael Ellerman +Signed-off-by: Greg Kroah-Hartman + +--- + arch/powerpc/platforms/pseries/mobility.c | 44 +++++++++++++++--------------- + 1 file changed, 23 insertions(+), 21 deletions(-) + +--- a/arch/powerpc/platforms/pseries/mobility.c ++++ b/arch/powerpc/platforms/pseries/mobility.c +@@ -25,10 +25,10 @@ + static struct kobject *mobility_kobj; + + struct update_props_workarea { +- u32 phandle; +- u32 state; +- u64 reserved; +- u32 nprops; ++ __be32 phandle; ++ __be32 state; ++ __be64 reserved; ++ __be32 nprops; + } __packed; + + #define NODE_ACTION_MASK 0xff000000 +@@ -54,11 +54,11 @@ static int mobility_rtas_call(int token, + return rc; + } + +-static int delete_dt_node(u32 phandle) ++static int delete_dt_node(__be32 phandle) + { + struct device_node *dn; + +- dn = of_find_node_by_phandle(phandle); ++ dn = of_find_node_by_phandle(be32_to_cpu(phandle)); + if (!dn) + return -ENOENT; + +@@ -127,7 +127,7 @@ static int update_dt_property(struct dev + return 0; + } + +-static int update_dt_node(u32 phandle, s32 scope) ++static int update_dt_node(__be32 phandle, s32 scope) + { + struct update_props_workarea *upwa; + struct device_node *dn; +@@ -136,6 +136,7 @@ static int update_dt_node(u32 phandle, s + char *prop_data; + char *rtas_buf; + int update_properties_token; ++ u32 nprops; + u32 vd; + + update_properties_token = rtas_token("ibm,update-properties"); +@@ -146,7 +147,7 @@ static int update_dt_node(u32 phandle, s + if (!rtas_buf) + return -ENOMEM; + +- dn = of_find_node_by_phandle(phandle); ++ dn = of_find_node_by_phandle(be32_to_cpu(phandle)); + if (!dn) { + kfree(rtas_buf); + return -ENOENT; +@@ -162,6 +163,7 @@ static int update_dt_node(u32 phandle, s + break; + + prop_data = rtas_buf + sizeof(*upwa); ++ nprops = be32_to_cpu(upwa->nprops); + + /* On the first call to ibm,update-properties for a node the + * the first property value descriptor contains an empty +@@ -170,17 +172,17 @@ static int update_dt_node(u32 phandle, s + */ + if (*prop_data == 0) { + prop_data++; +- vd = *(u32 *)prop_data; ++ vd = be32_to_cpu(*(__be32 *)prop_data); + prop_data += vd + sizeof(vd); +- upwa->nprops--; ++ nprops--; + } + +- for (i = 0; i < upwa->nprops; i++) { ++ for (i = 0; i < nprops; i++) { + char *prop_name; + + prop_name = prop_data; + prop_data += strlen(prop_name) + 1; +- vd = *(u32 *)prop_data; ++ vd = be32_to_cpu(*(__be32 *)prop_data); + prop_data += sizeof(vd); + + switch (vd) { +@@ -212,13 +214,13 @@ static int update_dt_node(u32 phandle, s + return 0; + } + +-static int add_dt_node(u32 parent_phandle, u32 drc_index) ++static int add_dt_node(__be32 parent_phandle, __be32 drc_index) + { + struct device_node *dn; + struct device_node *parent_dn; + int rc; + +- parent_dn = of_find_node_by_phandle(parent_phandle); ++ parent_dn = of_find_node_by_phandle(be32_to_cpu(parent_phandle)); + if (!parent_dn) + return -ENOENT; + +@@ -237,7 +239,7 @@ static int add_dt_node(u32 parent_phandl + int pseries_devicetree_update(s32 scope) + { + char *rtas_buf; +- u32 *data; ++ __be32 *data; + int update_nodes_token; + int rc; + +@@ -254,17 +256,17 @@ int pseries_devicetree_update(s32 scope) + if (rc && rc != 1) + break; + +- data = (u32 *)rtas_buf + 4; +- while (*data & NODE_ACTION_MASK) { ++ data = (__be32 *)rtas_buf + 4; ++ while (be32_to_cpu(*data) & NODE_ACTION_MASK) { + int i; +- u32 action = *data & NODE_ACTION_MASK; +- int node_count = *data & NODE_COUNT_MASK; ++ u32 action = be32_to_cpu(*data) & NODE_ACTION_MASK; ++ u32 node_count = be32_to_cpu(*data) & NODE_COUNT_MASK; + + data++; + + for (i = 0; i < node_count; i++) { +- u32 phandle = *data++; +- u32 drc_index; ++ __be32 phandle = *data++; ++ __be32 drc_index; + + switch (action) { + case DELETE_DT_NODE: diff --git a/queue-3.19/regulator-palmas-correct-tps659038-register-definition-for-regen2.patch b/queue-3.19/regulator-palmas-correct-tps659038-register-definition-for-regen2.patch new file mode 100644 index 00000000000..edf3ebf256c --- /dev/null +++ b/queue-3.19/regulator-palmas-correct-tps659038-register-definition-for-regen2.patch @@ -0,0 +1,47 @@ +From e03826d5045e81a66a4fad7be9a8ecdaeb7911cf Mon Sep 17 00:00:00 2001 +From: Keerthy +Date: Tue, 17 Mar 2015 15:56:04 +0530 +Subject: regulator: palmas: Correct TPS659038 register definition for REGEN2 + +From: Keerthy + +commit e03826d5045e81a66a4fad7be9a8ecdaeb7911cf upstream. + +The register offset for REGEN2_CTRL in different for TPS659038 chip as when +compared with other Palmas family PMICs. In the case of TPS659038 the wrong +offset pointed to PLLEN_CTRL and was causing a hang. Correcting the same. + +Signed-off-by: Keerthy +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/regulator/palmas-regulator.c | 4 ++++ + include/linux/mfd/palmas.h | 3 +++ + 2 files changed, 7 insertions(+) + +--- a/drivers/regulator/palmas-regulator.c ++++ b/drivers/regulator/palmas-regulator.c +@@ -1572,6 +1572,10 @@ static int palmas_regulators_probe(struc + if (!pmic) + return -ENOMEM; + ++ if (of_device_is_compatible(node, "ti,tps659038-pmic")) ++ palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr = ++ TPS659038_REGEN2_CTRL; ++ + pmic->dev = &pdev->dev; + pmic->palmas = palmas; + palmas->pmic = pmic; +--- a/include/linux/mfd/palmas.h ++++ b/include/linux/mfd/palmas.h +@@ -2999,6 +2999,9 @@ enum usb_irq_events { + #define PALMAS_GPADC_TRIM15 0x0E + #define PALMAS_GPADC_TRIM16 0x0F + ++/* TPS659038 regen2_ctrl offset iss different from palmas */ ++#define TPS659038_REGEN2_CTRL 0x12 ++ + /* TPS65917 Interrupt registers */ + + /* Registers for function INTERRUPT */ diff --git a/queue-3.19/series b/queue-3.19/series index 09962717d2e..3e107474a00 100644 --- a/queue-3.19/series +++ b/queue-3.19/series @@ -65,3 +65,11 @@ spi-qup-fix-cs-num-dt-property-parsing.patch spi-dw-mid-clear-busy-flag-fist-and-test-other-one.patch spi-trigger-trace-event-for-message-done-before-mesg-complete.patch hfsplus-fix-b-tree-corruption-after-insertion-at-position-0.patch +powerpc-book3s-fix-the-mce-code-to-use-config_kvm_book3s_64_handler.patch +regulator-palmas-correct-tps659038-register-definition-for-regen2.patch +arm64-use-the-reserved-ttbr0-if-context-switching-to-the-init_mm.patch +arm64-percpu-make-this_cpu-accessors-pre-empt-safe.patch +powerpc-pseries-little-endian-fixes-for-post-mobility-device-tree-update.patch +powerpc-mpc85xx-add-ranges-to-etsec2-nodes.patch +net-ethernet-pcnet32-setup-the-sram-and-nouflo-on-am79c97-3-5.patch +mfd-kempld-core-fix-callback-return-value-check.patch