From: tnfchris Date: Mon, 11 Feb 2019 16:54:18 +0000 (+0000) Subject: Arm: Update tests after register allocation changes. (PR/target 88560) X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=dd9bf21a80f9a035fa8667abf80b02b167a4e015;p=thirdparty%2Fgcc.git Arm: Update tests after register allocation changes. (PR/target 88560) After the register allocator changes of r268705 we need to update a few tests with new output. In all cases the compiler is now generating the expected code, since the tests are all float16 testcases using a hard-floar abi, we expect that actual fp16 instructions are used rather than using integer loads and stores. Because of we also save on some mov.f16s that were being emitted before to move between the two. The aapcs cases now match the f32 cases in using floating point operations. gcc/testsuite/Changelog PR middle-end/88560 * gcc.target/arm/armv8_2-fp16-move-1.c: Update assembler scans. * gcc.target/arm/fp16-aapcs-1.c: Likewise. * gcc.target/arm/fp16-aapcs-3.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@268772 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 78aa1bc3c4c8..c3b84bf0ff42 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2019-02-11 Tamar Christina + + PR middle-end/88560 + * gcc.target/arm/armv8_2-fp16-move-1.c: Update assembler scans. + * gcc.target/arm/fp16-aapcs-3.c: Likewise. + * gcc.target/arm/fp16-aapcs-1.c: Likewise. + 2019-02-11 Bill Schmidt * gcc.target/powerpc/vec-sld-modulo.c: New. diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c index 56d87eb6f716..2321dd38cc6d 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-move-1.c @@ -16,7 +16,6 @@ test_load_2 (__fp16* a, int i) return a[i]; } -/* { dg-final { scan-assembler-times {vld1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 2 } } */ void test_store_1 (__fp16* a, __fp16 b) @@ -30,7 +29,6 @@ test_store_2 (__fp16* a, int i, __fp16 b) a[i] = b; } -/* { dg-final { scan-assembler-times {vst1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 2 } } */ __fp16 test_load_store_1 (__fp16* a, int i, __fp16* b) @@ -44,8 +42,9 @@ test_load_store_2 (__fp16* a, int i, __fp16* b) a[i] = b[i + 2]; return a[i]; } -/* { dg-final { scan-assembler-times {ldrh\tr[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {strh\tr[0-9]+} 2 } } */ + +/* { dg-final { scan-assembler-times {vst1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 3 } } */ +/* { dg-final { scan-assembler-times {vld1\.16\t\{d[0-9]+\[[0-9]+\]\}, \[r[0-9]+\]} 3 } } */ __fp16 test_select_1 (int sel, __fp16 a, __fp16 b) @@ -102,7 +101,7 @@ test_select_8 (__fp16 a, __fp16 b, __fp16 c) /* { dg-final { scan-assembler-times {vselgt\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */ /* { dg-final { scan-assembler-times {vselge\.f16\ts[0-9]+, s[0-9]+, s[0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {vmov\.f16\ts[0-9]+, r[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmov\.f16} } } */ int test_compare_1 (__fp16 a, __fp16 b) diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c index b91168d43b38..0a0a60f35033 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c @@ -16,6 +16,7 @@ F (__fp16 a, __fp16 b, __fp16 c) return c; } -/* { dg-final { scan-assembler {vmov(\.f16)?\tr[0-9]+, s[0-9]+} } } */ -/* { dg-final { scan-assembler {vmov(\.f32)?\ts1, s0} } } */ -/* { dg-final { scan-assembler {vmov(\.f16)?\ts0, r[0-9]+} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s1} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts1, s0} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s2+} } } */ +/* { dg-final { scan-assembler-times {vmov\.f32\ts0, s[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c index 84fc0a0f5f06..56a3ae261843 100644 --- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c +++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-3.c @@ -16,6 +16,8 @@ F (__fp16 a, __fp16 b, __fp16 c) return c; } -/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-2]} 2 } } */ -/* { dg-final { scan-assembler-times {vmov.f32\ts1, s0} 1 } } */ -/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 2 } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s1} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts1, s0} } } */ +/* { dg-final { scan-assembler {vmov\.f32\ts[0-9]+, s2+} } } */ +/* { dg-final { scan-assembler-times {vmov\.f32\ts0, s[0-9]+} 2 } } */ +