From: Andrey Smirnov Date: Fri, 5 Apr 2019 17:30:02 +0000 (-0700) Subject: arm64: dts: imx8mq: Combine PCIE power domains X-Git-Tag: v5.2-rc1~45^2~1^2~11 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=de2a538b97a489bb67be7cdc44115d1c6a07e837;p=thirdparty%2Fkernel%2Flinux.git arm64: dts: imx8mq: Combine PCIE power domains According to NXP's FAE feedback and a comment in ATF firmware, PCIE1 and PCIE2 power domains can't really be used independently. Due to shared reset line both power domains have to be turned on at the same time. Account for that quirk by combining PCIE power domains into a single 'pgc_pcie' power domain. Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Reviewed-by: Fabio Estevam Cc: Shawn Guo Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Leonard Crestez Cc: "A.s. Dong" Cc: Richard Zhu Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 0235967d1a2ec..253d6d66af1af 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -472,9 +472,25 @@ reg = ; }; - pgc_pcie1: power-domain@1 { + /* + * As per comment in ATF source code: + * + * PCIE1 and PCIE2 share the + * same reset signal, if we + * power down PCIE2, PCIE1 + * will be held in reset too. + * + * So instead of creating two + * separate power domains for + * PCIE1 and PCIE2 we create a + * link between both and use + * it as a shared PCIE power + * domain. + */ + pgc_pcie: power-domain@1 { #power-domain-cells = <0>; reg = ; + power-domains = <&pgc_pcie2>; }; pgc_otg1: power-domain@2 {