From: Greg Kroah-Hartman Date: Sun, 16 Oct 2022 16:33:59 +0000 (+0200) Subject: 5.19-stable patches X-Git-Tag: v5.4.219~73 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=dee8461885b3912ea627af30dc6b6e1bbb16299b;p=thirdparty%2Fkernel%2Fstable-queue.git 5.19-stable patches added patches: drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch --- diff --git a/queue-5.19/drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch b/queue-5.19/drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch new file mode 100644 index 00000000000..d0aee1712a4 --- /dev/null +++ b/queue-5.19/drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch @@ -0,0 +1,53 @@ +From b2e3a1af8cce4117de06ff1a4eab0749753ede27 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 3 Oct 2022 14:15:43 +0300 +Subject: drm/i915: Fix watermark calculations for DG2 CCS+CC modifier +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit b2e3a1af8cce4117de06ff1a4eab0749753ede27 upstream. + +Take the DG2 CCS+CC modifier into account when calculating the +watermarks. Othwerwise we'll calculate the watermarks thinking this +tile-4 modifier is linear. + +The rc_surface part is actually a nop since that is not used +for any glk+ platform. + +Cc: stable@vger.kernel.org +Fixes: 680025dcc400 ("drm/i915/dg2: Add support for DG2 clear color compression") +Reviewed-by: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20221003111544.8007-6-ville.syrjala@linux.intel.com +(cherry picked from commit 334810f82024815283a6e7febd3d2de1fed6c232) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -5312,7 +5312,8 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || + modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS || +- modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; + wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; + wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || +@@ -5320,7 +5321,8 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || + modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS || +- modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC; + wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); + + wp->width = width; diff --git a/queue-5.19/drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch b/queue-5.19/drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch new file mode 100644 index 00000000000..7cd41cc99a7 --- /dev/null +++ b/queue-5.19/drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch @@ -0,0 +1,53 @@ +From ccfa6d35f9233702c924316cdf40c05b6ce88113 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 3 Oct 2022 14:15:42 +0300 +Subject: drm/i915: Fix watermark calculations for DG2 CCS modifiers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit ccfa6d35f9233702c924316cdf40c05b6ce88113 upstream. + +Take the DG2 CCS modifiers into account when calculating the +watermarks. Othwerwise we'll calculate the watermarks thinking these +tile-4 modifiers are linear. + +The rc_surface part is actually a nop since that is not used +for any glk+ platform. + +Cc: stable@vger.kernel.org +Fixes: 4c3afa72138c ("drm/i915/dg2: Add support for DG2 render and media compression") +Reviewed-by: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20221003111544.8007-5-ville.syrjala@linux.intel.com +(cherry picked from commit f25d9f81a8e09ace4f04106995550bae1f522143) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/intel_pm.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -5310,13 +5310,17 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; + wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; + wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_RC_CCS || ++ modifier == I915_FORMAT_MOD_4_TILED_DG2_MC_CCS; + wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); + + wp->width = width; diff --git a/queue-5.19/drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch b/queue-5.19/drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch new file mode 100644 index 00000000000..0aad7396682 --- /dev/null +++ b/queue-5.19/drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch @@ -0,0 +1,50 @@ +From 070a2855900de17b1e11a0dc35af9794e80f1a28 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 3 Oct 2022 14:15:41 +0300 +Subject: drm/i915: Fix watermark calculations for gen12+ CCS+CC modifier +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 070a2855900de17b1e11a0dc35af9794e80f1a28 upstream. + +Take the gen12+ CCS+CC modifier into account when calculating the +watermarks. Othwerwise we'll calculate the watermarks thinking this +Y-tiled modifier is linear. + +The rc_surface part is actually a nop since that is not used +for any glk+ platform. + +Cc: stable@vger.kernel.org +Fixes: d1e2775e9b96 ("drm/i915/tgl: Add Clear Color support for TGL Render Decompression") +Reviewed-by: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20221003111544.8007-4-ville.syrjala@linux.intel.com +(cherry picked from commit a627455bbe50a111475d7a42beb58fa64bd96c83) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -5309,12 +5309,14 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; + wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; + wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC; + wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); + + wp->width = width; diff --git a/queue-5.19/drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch b/queue-5.19/drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch new file mode 100644 index 00000000000..f69ac55b88d --- /dev/null +++ b/queue-5.19/drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch @@ -0,0 +1,51 @@ +From 484b2b9281000274ef7c5cb0a9ebc5da6f5c281c Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Mon, 3 Oct 2022 14:15:40 +0300 +Subject: drm/i915: Fix watermark calculations for gen12+ MC CCS modifier +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 484b2b9281000274ef7c5cb0a9ebc5da6f5c281c upstream. + +Take the gen12+ MC CCS modifier into account when calculating the +watermarks. Othwerwise we'll calculate the watermarks thinking this +Y-tiled modifier is linear. + +The rc_surface part is actually a nop since that is not used +for any glk+ platform. + +v2: Split RC CCS vs. MC CCS to separate patches + +Cc: stable@vger.kernel.org +Fixes: 2dfbf9d2873a ("drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine") +Reviewed-by: Juha-Pekka Heikkila +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20221003111544.8007-3-ville.syrjala@linux.intel.com +(cherry picked from commit 91c9651425fe955b1387f3637607dda005f3f710) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/intel_pm.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_pm.c ++++ b/drivers/gpu/drm/i915/intel_pm.c +@@ -5308,11 +5308,13 @@ skl_compute_wm_params(const struct intel + modifier == I915_FORMAT_MOD_Yf_TILED || + modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; + wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; + wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || + modifier == I915_FORMAT_MOD_Yf_TILED_CCS || +- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS; ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || ++ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; + wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); + + wp->width = width; diff --git a/queue-5.19/series b/queue-5.19/series index 51f063dc7a2..e58687757d2 100644 --- a/queue-5.19/series +++ b/queue-5.19/series @@ -166,3 +166,7 @@ drm-nouveau-kms-nv140-disable-interlacing.patch drm-nouveau-fix-a-use-after-free-in-nouveau_gem_prime_import_sg_table.patch drm-i915-gt-use-i915_vm_put-on-ppgtt_create-error-paths.patch drm-i915-fix-watermark-calculations-for-gen12-rc-ccs-modifier.patch +drm-i915-fix-watermark-calculations-for-gen12-mc-ccs-modifier.patch +drm-i915-fix-watermark-calculations-for-gen12-ccs-cc-modifier.patch +drm-i915-fix-watermark-calculations-for-dg2-ccs-modifiers.patch +drm-i915-fix-watermark-calculations-for-dg2-ccs-cc-modifier.patch