From: Shengjiu Wang Date: Fri, 1 Jul 2022 09:32:40 +0000 (+0800) Subject: ASoC: dt-bindings: fsl_spdif: Add two PLL clock source X-Git-Tag: v6.0-rc1~93^2~8^2~37^2~19^2~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=df0835a810c1585bd54ffb10db92b455e922c7ec;p=thirdparty%2Fkernel%2Flinux.git ASoC: dt-bindings: fsl_spdif: Add two PLL clock source Add two PLL clock source, they are the parent clocks of root clock one is for 8kHz series rates, another one is for 11kHz series rates. They are optional clocks, if there are such clocks, then driver can switch between them for supporting more accurate rates. Signed-off-by: Shengjiu Wang Acked-by: Rob Herring Link: https://lore.kernel.org/r/1656667961-1799-6-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown --- diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml index f226ec13167ad..1d64e8337aa4b 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml @@ -58,6 +58,8 @@ properties: slave of the Shared Peripheral Bus and when two or more bus masters (CPU, DMA or DSP) try to access it. This property is optional depending on the SoC design. + - description: PLL clock source for 8kHz series rate, optional. + - description: PLL clock source for 11khz series rate, optional. minItems: 9 clock-names: @@ -72,6 +74,8 @@ properties: - const: rxtx6 - const: rxtx7 - const: spba + - const: pll8k + - const: pll11k minItems: 9 big-endian: