From: Sasha Levin Date: Wed, 17 Apr 2024 17:16:41 +0000 (-0400) Subject: Fixes for 6.1 X-Git-Tag: v5.15.157~91 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=df64f132b4a82da3810f79a516034e67200692ee;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 6.1 Signed-off-by: Sasha Levin --- diff --git a/queue-6.1/drm-amd-display-do-not-recursively-call-manual-trigg.patch b/queue-6.1/drm-amd-display-do-not-recursively-call-manual-trigg.patch new file mode 100644 index 00000000000..7c9960607c1 --- /dev/null +++ b/queue-6.1/drm-amd-display-do-not-recursively-call-manual-trigg.patch @@ -0,0 +1,40 @@ +From f89378511ab34506071b6943d1e2bef2122d54fd Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 21 Mar 2024 13:49:43 -0400 +Subject: drm/amd/display: Do not recursively call manual trigger programming + +From: Dillon Varone + +[ Upstream commit 953927587f37b731abdeabe46ad44a3b3ec67a52 ] + +[WHY&HOW] +We should not be recursively calling the manual trigger programming function when +FAMS is not in use. + +Cc: stable@vger.kernel.org +Reviewed-by: Alvin Lee +Acked-by: Hamza Mahfooz +Signed-off-by: Dillon Varone +Signed-off-by: Alex Deucher +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 3 --- + 1 file changed, 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c +index a974f86e718a8..37c645a882dd8 100644 +--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c +@@ -216,9 +216,6 @@ static void optc32_setup_manual_trigger(struct timing_generator *optc) + OTG_V_TOTAL_MAX_SEL, 1, + OTG_FORCE_LOCK_ON_EVENT, 0, + OTG_SET_V_TOTAL_MIN_MASK, (1 << 1)); /* TRIGA */ +- +- // Setup manual flow control for EOF via TRIG_A +- optc->funcs->setup_manual_trigger(optc); + } + } + +-- +2.43.0 + diff --git a/queue-6.1/drm-amdgpu-fix-incorrect-active-rb-bitmap-for-gfx11.patch b/queue-6.1/drm-amdgpu-fix-incorrect-active-rb-bitmap-for-gfx11.patch new file mode 100644 index 00000000000..c8711c48561 --- /dev/null +++ b/queue-6.1/drm-amdgpu-fix-incorrect-active-rb-bitmap-for-gfx11.patch @@ -0,0 +1,130 @@ +From 7217782b08f2c1775e40e23b7f033a4fc281f05b Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 20 Feb 2023 09:06:53 +0800 +Subject: drm/amdgpu: fix incorrect active rb bitmap for gfx11 + +From: Hawking Zhang + +[ Upstream commit f9c35f4fffc6cb5bbb23f546f48c045aef012518 ] + +GFX v11 changes RB_BACKEND_DISABLE related registers +from per SA to global ones. The approach to query active +rb bitmap needs to be changed accordingly. Query per +SE setting returns wrong active RB bitmap especially +in the case when some of SA are disabled. With the new +approach, driver will generate the active rb bitmap +based on active SA bitmap and global active RB bitmap. + +Signed-off-by: Hawking Zhang +Reviewed-by: Likun Gao +Signed-off-by: Alex Deucher +Stable-dep-of: bbca7f414ae9 ("drm/amdgpu: fix incorrect number of active RBs for gfx11") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 78 +++++++++++++++++--------- + 1 file changed, 52 insertions(+), 26 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +index 66a6f7a37ebcf..ec40f88da00c3 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -1531,44 +1531,70 @@ static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, + WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data); + } + +-static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) ++static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev) + { +- u32 data, mask; ++ u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; ++ ++ gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE); ++ gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, ++ CC_GC_SA_UNIT_DISABLE, ++ SA_DISABLE); ++ gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE); ++ gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, ++ GC_USER_SA_UNIT_DISABLE, ++ SA_DISABLE); ++ sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * ++ adev->gfx.config.max_shader_engines); + +- data = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); +- data |= RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); ++ return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); ++} + +- data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; +- data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; ++static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev) ++{ ++ u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask; ++ u32 rb_mask; + +- mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / +- adev->gfx.config.max_sh_per_se); ++ gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE); ++ gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask, ++ CC_RB_BACKEND_DISABLE, ++ BACKEND_DISABLE); ++ gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE); ++ gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask, ++ GC_USER_RB_BACKEND_DISABLE, ++ BACKEND_DISABLE); ++ rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se * ++ adev->gfx.config.max_shader_engines); + +- return (~data) & mask; ++ return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask)); + } + + static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) + { +- int i, j; +- u32 data; +- u32 active_rbs = 0; +- u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / +- adev->gfx.config.max_sh_per_se; ++ u32 rb_bitmap_width_per_sa; ++ u32 max_sa; ++ u32 active_sa_bitmap; ++ u32 global_active_rb_bitmap; ++ u32 active_rb_bitmap = 0; ++ u32 i; + +- mutex_lock(&adev->grbm_idx_mutex); +- for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { +- for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { +- gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff); +- data = gfx_v11_0_get_rb_active_bitmap(adev); +- active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * +- rb_bitmap_width_per_sh); +- } ++ /* query sa bitmap from SA_UNIT_DISABLE registers */ ++ active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev); ++ /* query rb bitmap from RB_BACKEND_DISABLE registers */ ++ global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev); ++ ++ /* generate active rb bitmap according to active sa bitmap */ ++ max_sa = adev->gfx.config.max_shader_engines * ++ adev->gfx.config.max_sh_per_se; ++ rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se / ++ adev->gfx.config.max_sh_per_se; ++ for (i = 0; i < max_sa; i++) { ++ if (active_sa_bitmap & (1 << i)) ++ active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); + } +- gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); +- mutex_unlock(&adev->grbm_idx_mutex); + +- adev->gfx.config.backend_enable_mask = active_rbs; +- adev->gfx.config.num_rbs = hweight32(active_rbs); ++ active_rb_bitmap |= global_active_rb_bitmap; ++ adev->gfx.config.backend_enable_mask = active_rb_bitmap; ++ adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); + } + + #define DEFAULT_SH_MEM_BASES (0x6000) +-- +2.43.0 + diff --git a/queue-6.1/drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gf.patch b/queue-6.1/drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gf.patch new file mode 100644 index 00000000000..767c8564bc7 --- /dev/null +++ b/queue-6.1/drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gf.patch @@ -0,0 +1,37 @@ +From c457d1f825d2f7430d111ab0afcfd45a74fcc9d3 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 3 Apr 2024 17:28:44 +0800 +Subject: drm/amdgpu: fix incorrect number of active RBs for gfx11 + +From: Tim Huang + +[ Upstream commit bbca7f414ae9a12ea231cdbafd79c607e3337ea8 ] + +The RB bitmap should be global active RB bitmap & +active RB bitmap based on active SA. + +Signed-off-by: Tim Huang +Reviewed-by: Yifan Zhang +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +index ec40f88da00c3..5a5787bfbce7f 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -1592,7 +1592,7 @@ static void gfx_v11_0_setup_rb(struct amdgpu_device *adev) + active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa)); + } + +- active_rb_bitmap |= global_active_rb_bitmap; ++ active_rb_bitmap &= global_active_rb_bitmap; + adev->gfx.config.backend_enable_mask = active_rb_bitmap; + adev->gfx.config.num_rbs = hweight32(active_rb_bitmap); + } +-- +2.43.0 + diff --git a/queue-6.1/drm-vmwgfx-enable-dma-mappings-with-sev.patch b/queue-6.1/drm-vmwgfx-enable-dma-mappings-with-sev.patch new file mode 100644 index 00000000000..b9bf68b0204 --- /dev/null +++ b/queue-6.1/drm-vmwgfx-enable-dma-mappings-with-sev.patch @@ -0,0 +1,54 @@ +From d28663255b361f779868e222ba5b4c8d80168fdc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sun, 7 Apr 2024 22:28:02 -0400 +Subject: drm/vmwgfx: Enable DMA mappings with SEV + +From: Zack Rusin + +[ Upstream commit 4c08f01934ab67d1d283d5cbaa52b923abcfe4cd ] + +Enable DMA mappings in vmwgfx after TTM has been fixed in commit +3bf3710e3718 ("drm/ttm: Add a generic TTM memcpy move for page-based iomem") + +This enables full guest-backed memory support and in particular allows +usage of screen targets as the presentation mechanism. + +Signed-off-by: Zack Rusin +Reported-by: Ye Li +Tested-by: Ye Li +Fixes: 3b0d6458c705 ("drm/vmwgfx: Refuse DMA operation when SEV encryption is active") +Cc: Broadcom internal kernel review list +Cc: dri-devel@lists.freedesktop.org +Cc: # v6.6+ +Reviewed-by: Martin Krastev +Link: https://patchwork.freedesktop.org/patch/msgid/20240408022802.358641-1-zack.rusin@broadcom.com +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/vmwgfx/vmwgfx_drv.c | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +index 9d7a1b710f48f..53f63ad656a41 100644 +--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c ++++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +@@ -663,11 +663,12 @@ static int vmw_dma_select_mode(struct vmw_private *dev_priv) + [vmw_dma_map_populate] = "Caching DMA mappings.", + [vmw_dma_map_bind] = "Giving up DMA mappings early."}; + +- /* TTM currently doesn't fully support SEV encryption. */ +- if (cc_platform_has(CC_ATTR_MEM_ENCRYPT)) +- return -EINVAL; +- +- if (vmw_force_coherent) ++ /* ++ * When running with SEV we always want dma mappings, because ++ * otherwise ttm tt pool pages will bounce through swiotlb running ++ * out of available space. ++ */ ++ if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT)) + dev_priv->map_mode = vmw_dma_alloc_coherent; + else if (vmw_restrict_iommu) + dev_priv->map_mode = vmw_dma_map_bind; +-- +2.43.0 + diff --git a/queue-6.1/series b/queue-6.1/series new file mode 100644 index 00000000000..a0b0e292fb9 --- /dev/null +++ b/queue-6.1/series @@ -0,0 +1,4 @@ +drm-vmwgfx-enable-dma-mappings-with-sev.patch +drm-amdgpu-fix-incorrect-active-rb-bitmap-for-gfx11.patch +drm-amdgpu-fix-incorrect-number-of-active-rbs-for-gf.patch +drm-amd-display-do-not-recursively-call-manual-trigg.patch