From: Claudiu Beznea Date: Sat, 19 Oct 2024 08:47:28 +0000 (+0300) Subject: clk: renesas: r9a08g045: Add power domain for RTC X-Git-Tag: v6.13-rc1~110^2~2^5^2~4 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e200b06d8ecaa70798f45f815b2cac280a7c1b20;p=thirdparty%2Flinux.git clk: renesas: r9a08g045: Add power domain for RTC The RTC and VBATTB don't share the MSTOP control bit (but only the bus clock and the reset signal). As the MSTOP control is modeled though power domains add power domain support for the RTC device available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20241019084738.3370489-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c index f5f454832bb53..b2ae8cdc4723e 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -309,6 +309,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), GENPD_FLAG_ALWAYS_ON), + DEF_PD("rtc", R9A08G045_PD_RTC, + DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0), }; const struct rzg2l_cpg_info r9a08g045_cpg_info = {