From: Greg Kroah-Hartman Date: Mon, 24 Jan 2022 13:51:22 +0000 (+0100) Subject: 4.14-stable patches X-Git-Tag: v4.4.300~51 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e25e0bb424de2ac9e5aa97e2c4a01ecef8d8cb06;p=thirdparty%2Fkernel%2Fstable-queue.git 4.14-stable patches added patches: bcmgenet-add-wol-irq-check.patch dmaengine-at_xdmac-fix-at_xdmac_lld-struct-definition.patch dmaengine-at_xdmac-fix-lld-view-setting.patch dmaengine-at_xdmac-print-debug-message-after-realeasing-the-lock.patch net_sched-restore-mpu-xxx-handling.patch --- diff --git a/queue-4.14/bcmgenet-add-wol-irq-check.patch b/queue-4.14/bcmgenet-add-wol-irq-check.patch new file mode 100644 index 00000000000..409d95521b7 --- /dev/null +++ b/queue-4.14/bcmgenet-add-wol-irq-check.patch @@ -0,0 +1,42 @@ +From 9deb48b53e7f4056c2eaa2dc2ee3338df619e4f6 Mon Sep 17 00:00:00 2001 +From: Sergey Shtylyov +Date: Thu, 13 Jan 2022 22:46:07 +0300 +Subject: bcmgenet: add WOL IRQ check + +From: Sergey Shtylyov + +commit 9deb48b53e7f4056c2eaa2dc2ee3338df619e4f6 upstream. + +The driver neglects to check the result of platform_get_irq_optional()'s +call and blithely passes the negative error codes to devm_request_irq() +(which takes *unsigned* IRQ #), causing it to fail with -EINVAL. +Stop calling devm_request_irq() with the invalid IRQ #s. + +Fixes: 8562056f267d ("net: bcmgenet: request Wake-on-LAN interrupt") +Signed-off-by: Sergey Shtylyov +Acked-by: Florian Fainelli +Signed-off-by: David S. Miller +Signed-off-by: Greg Kroah-Hartman +--- + drivers/net/ethernet/broadcom/genet/bcmgenet.c | 10 ++++++---- + 1 file changed, 6 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/broadcom/genet/bcmgenet.c ++++ b/drivers/net/ethernet/broadcom/genet/bcmgenet.c +@@ -3519,10 +3519,12 @@ static int bcmgenet_probe(struct platfor + + /* Request the WOL interrupt and advertise suspend if available */ + priv->wol_irq_disabled = true; +- err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, +- dev->name, priv); +- if (!err) +- device_set_wakeup_capable(&pdev->dev, 1); ++ if (priv->wol_irq > 0) { ++ err = devm_request_irq(&pdev->dev, priv->wol_irq, ++ bcmgenet_wol_isr, 0, dev->name, priv); ++ if (!err) ++ device_set_wakeup_capable(&pdev->dev, 1); ++ } + + /* Set the needed headroom to account for any possible + * features enabling/disabling at runtime diff --git a/queue-4.14/dmaengine-at_xdmac-fix-at_xdmac_lld-struct-definition.patch b/queue-4.14/dmaengine-at_xdmac-fix-at_xdmac_lld-struct-definition.patch new file mode 100644 index 00000000000..e127648ff36 --- /dev/null +++ b/queue-4.14/dmaengine-at_xdmac-fix-at_xdmac_lld-struct-definition.patch @@ -0,0 +1,50 @@ +From 912f7c6f7fac273f40e621447cf17d14b50d6e5b Mon Sep 17 00:00:00 2001 +From: Tudor Ambarus +Date: Wed, 15 Dec 2021 13:01:13 +0200 +Subject: dmaengine: at_xdmac: Fix at_xdmac_lld struct definition + +From: Tudor Ambarus + +commit 912f7c6f7fac273f40e621447cf17d14b50d6e5b upstream. + +The hardware channel next descriptor view structure contains just +fields of 32 bits, while dma_addr_t can be of type u64 or u32 +depending on CONFIG_ARCH_DMA_ADDR_T_64BIT. Force u32 to comply with +what the hardware expects. + +Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") +Signed-off-by: Tudor Ambarus +Link: https://lore.kernel.org/r/20211215110115.191749-11-tudor.ambarus@microchip.com +Signed-off-by: Vinod Koul +Signed-off-by: Greg Kroah-Hartman +--- + drivers/dma/at_xdmac.c | 18 +++++++++--------- + 1 file changed, 9 insertions(+), 9 deletions(-) + +--- a/drivers/dma/at_xdmac.c ++++ b/drivers/dma/at_xdmac.c +@@ -232,15 +232,15 @@ struct at_xdmac { + + /* Linked List Descriptor */ + struct at_xdmac_lld { +- dma_addr_t mbr_nda; /* Next Descriptor Member */ +- u32 mbr_ubc; /* Microblock Control Member */ +- dma_addr_t mbr_sa; /* Source Address Member */ +- dma_addr_t mbr_da; /* Destination Address Member */ +- u32 mbr_cfg; /* Configuration Register */ +- u32 mbr_bc; /* Block Control Register */ +- u32 mbr_ds; /* Data Stride Register */ +- u32 mbr_sus; /* Source Microblock Stride Register */ +- u32 mbr_dus; /* Destination Microblock Stride Register */ ++ u32 mbr_nda; /* Next Descriptor Member */ ++ u32 mbr_ubc; /* Microblock Control Member */ ++ u32 mbr_sa; /* Source Address Member */ ++ u32 mbr_da; /* Destination Address Member */ ++ u32 mbr_cfg; /* Configuration Register */ ++ u32 mbr_bc; /* Block Control Register */ ++ u32 mbr_ds; /* Data Stride Register */ ++ u32 mbr_sus; /* Source Microblock Stride Register */ ++ u32 mbr_dus; /* Destination Microblock Stride Register */ + }; + + /* 64-bit alignment needed to update CNDA and CUBC registers in an atomic way. */ diff --git a/queue-4.14/dmaengine-at_xdmac-fix-lld-view-setting.patch b/queue-4.14/dmaengine-at_xdmac-fix-lld-view-setting.patch new file mode 100644 index 00000000000..f6a25c5df26 --- /dev/null +++ b/queue-4.14/dmaengine-at_xdmac-fix-lld-view-setting.patch @@ -0,0 +1,41 @@ +From 1385eb4d14d447cc5d744bc2ac34f43be66c9963 Mon Sep 17 00:00:00 2001 +From: Tudor Ambarus +Date: Wed, 15 Dec 2021 13:01:12 +0200 +Subject: dmaengine: at_xdmac: Fix lld view setting + +From: Tudor Ambarus + +commit 1385eb4d14d447cc5d744bc2ac34f43be66c9963 upstream. + +AT_XDMAC_CNDC_NDVIEW_NDV3 was set even for AT_XDMAC_MBR_UBC_NDV2, +because of the wrong bit handling. Fix it. + +Fixes: ee0fe35c8dcd ("dmaengine: xdmac: Handle descriptor's view 3 registers") +Signed-off-by: Tudor Ambarus +Link: https://lore.kernel.org/r/20211215110115.191749-10-tudor.ambarus@microchip.com +Signed-off-by: Vinod Koul +Signed-off-by: Greg Kroah-Hartman +--- + drivers/dma/at_xdmac.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/dma/at_xdmac.c ++++ b/drivers/dma/at_xdmac.c +@@ -100,6 +100,7 @@ + #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */ + #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */ + #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */ ++#define AT_XDMAC_CNDC_NDVIEW_MASK GENMASK(28, 27) + #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */ + #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */ + #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */ +@@ -359,7 +360,8 @@ static void at_xdmac_start_xfer(struct a + */ + if (at_xdmac_chan_is_cyclic(atchan)) + reg = AT_XDMAC_CNDC_NDVIEW_NDV1; +- else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3) ++ else if ((first->lld.mbr_ubc & ++ AT_XDMAC_CNDC_NDVIEW_MASK) == AT_XDMAC_MBR_UBC_NDV3) + reg = AT_XDMAC_CNDC_NDVIEW_NDV3; + else + reg = AT_XDMAC_CNDC_NDVIEW_NDV2; diff --git a/queue-4.14/dmaengine-at_xdmac-print-debug-message-after-realeasing-the-lock.patch b/queue-4.14/dmaengine-at_xdmac-print-debug-message-after-realeasing-the-lock.patch new file mode 100644 index 00000000000..b1bc78af2ee --- /dev/null +++ b/queue-4.14/dmaengine-at_xdmac-print-debug-message-after-realeasing-the-lock.patch @@ -0,0 +1,38 @@ +From 5edc24ac876a928f36f407a0fcdb33b94a3a210f Mon Sep 17 00:00:00 2001 +From: Tudor Ambarus +Date: Wed, 15 Dec 2021 13:01:06 +0200 +Subject: dmaengine: at_xdmac: Print debug message after realeasing the lock + +From: Tudor Ambarus + +commit 5edc24ac876a928f36f407a0fcdb33b94a3a210f upstream. + +It is desirable to do the prints without the lock held if possible, so +move the print after the lock is released. + +Fixes: e1f7c9eee707 ("dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driver") +Signed-off-by: Tudor Ambarus +Link: https://lore.kernel.org/r/20211215110115.191749-4-tudor.ambarus@microchip.com +Signed-off-by: Vinod Koul +Signed-off-by: Greg Kroah-Hartman +--- + drivers/dma/at_xdmac.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/dma/at_xdmac.c ++++ b/drivers/dma/at_xdmac.c +@@ -424,10 +424,12 @@ static dma_cookie_t at_xdmac_tx_submit(s + spin_lock_irqsave(&atchan->lock, irqflags); + cookie = dma_cookie_assign(tx); + +- dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", +- __func__, atchan, desc); + list_add_tail(&desc->xfer_node, &atchan->xfers_list); + spin_unlock_irqrestore(&atchan->lock, irqflags); ++ ++ dev_vdbg(chan2dev(tx->chan), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n", ++ __func__, atchan, desc); ++ + return cookie; + } + diff --git a/queue-4.14/net_sched-restore-mpu-xxx-handling.patch b/queue-4.14/net_sched-restore-mpu-xxx-handling.patch new file mode 100644 index 00000000000..f81dcbb300c --- /dev/null +++ b/queue-4.14/net_sched-restore-mpu-xxx-handling.patch @@ -0,0 +1,99 @@ +From fb80445c438c78b40b547d12b8d56596ce4ccfeb Mon Sep 17 00:00:00 2001 +From: Kevin Bracey +Date: Wed, 12 Jan 2022 19:02:10 +0200 +Subject: net_sched: restore "mpu xxx" handling + +From: Kevin Bracey + +commit fb80445c438c78b40b547d12b8d56596ce4ccfeb upstream. + +commit 56b765b79e9a ("htb: improved accuracy at high rates") broke +"overhead X", "linklayer atm" and "mpu X" attributes. + +"overhead X" and "linklayer atm" have already been fixed. This restores +the "mpu X" handling, as might be used by DOCSIS or Ethernet shaping: + + tc class add ... htb rate X overhead 4 mpu 64 + +The code being fixed is used by htb, tbf and act_police. Cake has its +own mpu handling. qdisc_calculate_pkt_len still uses the size table +containing values adjusted for mpu by user space. + +iproute2 tc has always passed mpu into the kernel via a tc_ratespec +structure, but the kernel never directly acted on it, merely stored it +so that it could be read back by `tc class show`. + +Rather, tc would generate length-to-time tables that included the mpu +(and linklayer) in their construction, and the kernel used those tables. + +Since v3.7, the tables were no longer used. Along with "mpu", this also +broke "overhead" and "linklayer" which were fixed in 01cb71d2d47b +("net_sched: restore "overhead xxx" handling", v3.10) and 8a8e3d84b171 +("net_sched: restore "linklayer atm" handling", v3.11). + +"overhead" was fixed by simply restoring use of tc_ratespec::overhead - +this had originally been used by the kernel but was initially omitted +from the new non-table-based calculations. + +"linklayer" had been handled in the table like "mpu", but the mode was +not originally passed in tc_ratespec. The new implementation was made to +handle it by getting new versions of tc to pass the mode in an extended +tc_ratespec, and for older versions of tc the table contents were analysed +at load time to deduce linklayer. + +As "mpu" has always been given to the kernel in tc_ratespec, +accompanying the mpu-based table, we can restore system functionality +with no userspace change by making the kernel act on the tc_ratespec +value. + +Fixes: 56b765b79e9a ("htb: improved accuracy at high rates") +Signed-off-by: Kevin Bracey +Cc: Eric Dumazet +Cc: Jiri Pirko +Cc: Vimalkumar +Link: https://lore.kernel.org/r/20220112170210.1014351-1-kevin@bracey.fi +Signed-off-by: Jakub Kicinski +Signed-off-by: Greg Kroah-Hartman +--- + include/net/sch_generic.h | 5 +++++ + net/sched/sch_generic.c | 1 + + 2 files changed, 6 insertions(+) + +--- a/include/net/sch_generic.h ++++ b/include/net/sch_generic.h +@@ -885,6 +885,7 @@ struct psched_ratecfg { + u64 rate_bytes_ps; /* bytes per second */ + u32 mult; + u16 overhead; ++ u16 mpu; + u8 linklayer; + u8 shift; + }; +@@ -894,6 +895,9 @@ static inline u64 psched_l2t_ns(const st + { + len += r->overhead; + ++ if (len < r->mpu) ++ len = r->mpu; ++ + if (unlikely(r->linklayer == TC_LINKLAYER_ATM)) + return ((u64)(DIV_ROUND_UP(len,48)*53) * r->mult) >> r->shift; + +@@ -916,6 +920,7 @@ static inline void psched_ratecfg_getrat + res->rate = min_t(u64, r->rate_bytes_ps, ~0U); + + res->overhead = r->overhead; ++ res->mpu = r->mpu; + res->linklayer = (r->linklayer & TC_LINKLAYER_MASK); + } + +--- a/net/sched/sch_generic.c ++++ b/net/sched/sch_generic.c +@@ -1010,6 +1010,7 @@ void psched_ratecfg_precompute(struct ps + { + memset(r, 0, sizeof(*r)); + r->overhead = conf->overhead; ++ r->mpu = conf->mpu; + r->rate_bytes_ps = max_t(u64, conf->rate, rate64); + r->linklayer = (conf->linklayer & TC_LINKLAYER_MASK); + r->mult = 1; diff --git a/queue-4.14/series b/queue-4.14/series index 5eebd46e4a6..052973f59d2 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -173,3 +173,8 @@ net-axienet-fix-number-of-tx-ring-slots-for-available-check.patch netns-add-schedule-point-in-ops_exit_list.patch libcxgb-don-t-accidentally-set-rto_onlink-in-cxgb_find_route.patch dmaengine-at_xdmac-don-t-start-transactions-at-tx_submit-level.patch +dmaengine-at_xdmac-print-debug-message-after-realeasing-the-lock.patch +dmaengine-at_xdmac-fix-lld-view-setting.patch +dmaengine-at_xdmac-fix-at_xdmac_lld-struct-definition.patch +net_sched-restore-mpu-xxx-handling.patch +bcmgenet-add-wol-irq-check.patch