From: Greg Kroah-Hartman Date: Thu, 29 Nov 2018 08:03:26 +0000 (+0100) Subject: 4.14-stable patches X-Git-Tag: v4.19.6~38 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e331f16760d47d5ba100a5e1ba1d96c0db6608f8;p=thirdparty%2Fkernel%2Fstable-queue.git 4.14-stable patches added patches: xhci-add-quirk-to-workaround-the-errata-seen-on-cavium-thunder-x2-soc.patch xhci-allow-more-than-32-quirks.patch --- diff --git a/queue-4.14/arm64-remove-no-op-p-linker-flag.patch b/queue-4.14/arm64-remove-no-op-p-linker-flag.patch index 1cb72671b68..502ab5c9cce 100644 --- a/queue-4.14/arm64-remove-no-op-p-linker-flag.patch +++ b/queue-4.14/arm64-remove-no-op-p-linker-flag.patch @@ -29,11 +29,9 @@ Signed-off-by: Catalin Marinas Signed-off-by: Nick Desaulniers Signed-off-by: Sasha Levin --- - arch/arm64/Makefile | 2 +- + arch/arm64/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile -index 7318165cfc90..48f2b3657507 100644 --- a/arch/arm64/Makefile +++ b/arch/arm64/Makefile @@ -10,7 +10,7 @@ @@ -45,6 +43,3 @@ index 7318165cfc90..48f2b3657507 100644 CPPFLAGS_vmlinux.lds = -DTEXT_OFFSET=$(TEXT_OFFSET) GZFLAGS :=-9 --- -2.17.1 - diff --git a/queue-4.14/series b/queue-4.14/series index 10e3658f72a..a6bcd28455c 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -70,3 +70,5 @@ net-bcmgenet-fix-of-child-node-lookup.patch drm-mediatek-fix-of-sibling-node-lookup.patch power-supply-twl4030-charger-fix-of-sibling-node-loo.patch arm64-remove-no-op-p-linker-flag.patch +xhci-allow-more-than-32-quirks.patch +xhci-add-quirk-to-workaround-the-errata-seen-on-cavium-thunder-x2-soc.patch diff --git a/queue-4.14/xhci-add-quirk-to-workaround-the-errata-seen-on-cavium-thunder-x2-soc.patch b/queue-4.14/xhci-add-quirk-to-workaround-the-errata-seen-on-cavium-thunder-x2-soc.patch new file mode 100644 index 00000000000..62508ce6aab --- /dev/null +++ b/queue-4.14/xhci-add-quirk-to-workaround-the-errata-seen-on-cavium-thunder-x2-soc.patch @@ -0,0 +1,111 @@ +From 11644a7659529730eaf2f166efaabe7c3dc7af8c Mon Sep 17 00:00:00 2001 +From: "Cherian, George" +Date: Fri, 9 Nov 2018 17:21:22 +0200 +Subject: xhci: Add quirk to workaround the errata seen on Cavium Thunder-X2 Soc + +From: Cherian, George + +commit 11644a7659529730eaf2f166efaabe7c3dc7af8c upstream. + +Implement workaround for ThunderX2 Errata-129 (documented in +CN99XX Known Issues" available at Cavium support site). +As per ThunderX2errata-129, USB 2 device may come up as USB 1 +if a connection to a USB 1 device is followed by another connection to +a USB 2 device, the link will come up as USB 1 for the USB 2 device. + +Resolution: Reset the PHY after the USB 1 device is disconnected. +The PHY reset sequence is done using private registers in XHCI register +space. After the PHY is reset we check for the PLL lock status and retry +the operation if it fails. From our tests, retrying 4 times is sufficient. + +Add a new quirk flag XHCI_RESET_PLL_ON_DISCONNECT to invoke the workaround +in handle_xhci_port_status(). + +Cc: stable@vger.kernel.org +Signed-off-by: George Cherian +Signed-off-by: Mathias Nyman +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/usb/host/xhci-pci.c | 5 +++++ + drivers/usb/host/xhci-ring.c | 35 ++++++++++++++++++++++++++++++++++- + drivers/usb/host/xhci.h | 1 + + 3 files changed, 40 insertions(+), 1 deletion(-) + +--- a/drivers/usb/host/xhci-pci.c ++++ b/drivers/usb/host/xhci-pci.c +@@ -236,6 +236,11 @@ static void xhci_pci_quirks(struct devic + if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) + xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7; + ++ if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM || ++ pdev->vendor == PCI_VENDOR_ID_CAVIUM) && ++ pdev->device == 0x9026) ++ xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT; ++ + if (xhci->quirks & XHCI_RESET_ON_RESUME) + xhci_dbg_trace(xhci, trace_xhci_dbg_quirks, + "QUIRK: Resetting on resume"); +--- a/drivers/usb/host/xhci-ring.c ++++ b/drivers/usb/host/xhci-ring.c +@@ -1568,6 +1568,35 @@ static void handle_device_notification(s + usb_wakeup_notification(udev->parent, udev->portnum); + } + ++/* ++ * Quirk hanlder for errata seen on Cavium ThunderX2 processor XHCI ++ * Controller. ++ * As per ThunderX2errata-129 USB 2 device may come up as USB 1 ++ * If a connection to a USB 1 device is followed by another connection ++ * to a USB 2 device. ++ * ++ * Reset the PHY after the USB device is disconnected if device speed ++ * is less than HCD_USB3. ++ * Retry the reset sequence max of 4 times checking the PLL lock status. ++ * ++ */ ++static void xhci_cavium_reset_phy_quirk(struct xhci_hcd *xhci) ++{ ++ struct usb_hcd *hcd = xhci_to_hcd(xhci); ++ u32 pll_lock_check; ++ u32 retry_count = 4; ++ ++ do { ++ /* Assert PHY reset */ ++ writel(0x6F, hcd->regs + 0x1048); ++ udelay(10); ++ /* De-assert the PHY reset */ ++ writel(0x7F, hcd->regs + 0x1048); ++ udelay(200); ++ pll_lock_check = readl(hcd->regs + 0x1070); ++ } while (!(pll_lock_check & 0x1) && --retry_count); ++} ++ + static void handle_port_status(struct xhci_hcd *xhci, + union xhci_trb *event) + { +@@ -1725,9 +1754,13 @@ static void handle_port_status(struct xh + goto cleanup; + } + +- if (hcd->speed < HCD_USB3) ++ if (hcd->speed < HCD_USB3) { + xhci_test_and_clear_bit(xhci, port_array, faked_port_index, + PORT_PLC); ++ if ((xhci->quirks & XHCI_RESET_PLL_ON_DISCONNECT) && ++ (portsc & PORT_CSC) && !(portsc & PORT_CONNECT)) ++ xhci_cavium_reset_phy_quirk(xhci); ++ } + + cleanup: + /* Update event ring dequeue pointer before dropping the lock */ +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1838,6 +1838,7 @@ struct xhci_hcd { + #define XHCI_HW_LPM_DISABLE BIT_ULL(29) + #define XHCI_SUSPEND_DELAY BIT_ULL(30) + #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) ++#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34) + + unsigned int num_active_eps; + unsigned int limit_active_eps; diff --git a/queue-4.14/xhci-allow-more-than-32-quirks.patch b/queue-4.14/xhci-allow-more-than-32-quirks.patch new file mode 100644 index 00000000000..255aaba5baf --- /dev/null +++ b/queue-4.14/xhci-allow-more-than-32-quirks.patch @@ -0,0 +1,134 @@ +From 36b6857932f380fcb55c31ac75857e3e81dd583a Mon Sep 17 00:00:00 2001 +From: Marc Zyngier +Date: Wed, 23 May 2018 18:41:36 +0100 +Subject: xhci: Allow more than 32 quirks + +From: Marc Zyngier + +commit 36b6857932f380fcb55c31ac75857e3e81dd583a upstream. + +We now have 32 different quirks, and the field that holds them +is full. Let's bump it up to the next stage so that we can handle +some more... The type is now an unsigned long long, which is 64bit +on most architectures. + +We take this opportunity to change the quirks from using (1 << x) +to BIT_ULL(x). + +Tested-by: Domenico Andreoli +Signed-off-by: Marc Zyngier +Tested-by: Faiz Abbas +Tested-by: Domenico Andreoli +Acked-by: Mathias Nyman +Cc: "Cherian, George" +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/usb/host/xhci.c | 6 ++-- + drivers/usb/host/xhci.h | 64 ++++++++++++++++++++++++------------------------ + 2 files changed, 36 insertions(+), 34 deletions(-) + +--- a/drivers/usb/host/xhci.c ++++ b/drivers/usb/host/xhci.c +@@ -43,8 +43,8 @@ static int link_quirk; + module_param(link_quirk, int, S_IRUGO | S_IWUSR); + MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB"); + +-static unsigned int quirks; +-module_param(quirks, uint, S_IRUGO); ++static unsigned long long quirks; ++module_param(quirks, ullong, S_IRUGO); + MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default"); + + static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring) +@@ -4956,7 +4956,7 @@ int xhci_gen_setup(struct usb_hcd *hcd, + return retval; + xhci_dbg(xhci, "Called HCD init\n"); + +- xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%08x\n", ++ xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n", + xhci->hcc_params, xhci->hci_version, xhci->quirks); + + return 0; +--- a/drivers/usb/host/xhci.h ++++ b/drivers/usb/host/xhci.h +@@ -1794,12 +1794,12 @@ struct xhci_hcd { + #define XHCI_STATE_DYING (1 << 0) + #define XHCI_STATE_HALTED (1 << 1) + #define XHCI_STATE_REMOVING (1 << 2) +- unsigned int quirks; +-#define XHCI_LINK_TRB_QUIRK (1 << 0) +-#define XHCI_RESET_EP_QUIRK (1 << 1) +-#define XHCI_NEC_HOST (1 << 2) +-#define XHCI_AMD_PLL_FIX (1 << 3) +-#define XHCI_SPURIOUS_SUCCESS (1 << 4) ++ unsigned long long quirks; ++#define XHCI_LINK_TRB_QUIRK BIT_ULL(0) ++#define XHCI_RESET_EP_QUIRK BIT_ULL(1) ++#define XHCI_NEC_HOST BIT_ULL(2) ++#define XHCI_AMD_PLL_FIX BIT_ULL(3) ++#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4) + /* + * Certain Intel host controllers have a limit to the number of endpoint + * contexts they can handle. Ideally, they would signal that they can't handle +@@ -1809,33 +1809,35 @@ struct xhci_hcd { + * commands, reset device commands, disable slot commands, and address device + * commands. + */ +-#define XHCI_EP_LIMIT_QUIRK (1 << 5) +-#define XHCI_BROKEN_MSI (1 << 6) +-#define XHCI_RESET_ON_RESUME (1 << 7) +-#define XHCI_SW_BW_CHECKING (1 << 8) +-#define XHCI_AMD_0x96_HOST (1 << 9) +-#define XHCI_TRUST_TX_LENGTH (1 << 10) +-#define XHCI_LPM_SUPPORT (1 << 11) +-#define XHCI_INTEL_HOST (1 << 12) +-#define XHCI_SPURIOUS_REBOOT (1 << 13) +-#define XHCI_COMP_MODE_QUIRK (1 << 14) +-#define XHCI_AVOID_BEI (1 << 15) +-#define XHCI_PLAT (1 << 16) +-#define XHCI_SLOW_SUSPEND (1 << 17) +-#define XHCI_SPURIOUS_WAKEUP (1 << 18) ++#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5) ++#define XHCI_BROKEN_MSI BIT_ULL(6) ++#define XHCI_RESET_ON_RESUME BIT_ULL(7) ++#define XHCI_SW_BW_CHECKING BIT_ULL(8) ++#define XHCI_AMD_0x96_HOST BIT_ULL(9) ++#define XHCI_TRUST_TX_LENGTH BIT_ULL(10) ++#define XHCI_LPM_SUPPORT BIT_ULL(11) ++#define XHCI_INTEL_HOST BIT_ULL(12) ++#define XHCI_SPURIOUS_REBOOT BIT_ULL(13) ++#define XHCI_COMP_MODE_QUIRK BIT_ULL(14) ++#define XHCI_AVOID_BEI BIT_ULL(15) ++#define XHCI_PLAT BIT_ULL(16) ++#define XHCI_SLOW_SUSPEND BIT_ULL(17) ++#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18) + /* For controllers with a broken beyond repair streams implementation */ +-#define XHCI_BROKEN_STREAMS (1 << 19) +-#define XHCI_PME_STUCK_QUIRK (1 << 20) +-#define XHCI_MTK_HOST (1 << 21) +-#define XHCI_SSIC_PORT_UNUSED (1 << 22) +-#define XHCI_NO_64BIT_SUPPORT (1 << 23) +-#define XHCI_MISSING_CAS (1 << 24) ++#define XHCI_BROKEN_STREAMS BIT_ULL(19) ++#define XHCI_PME_STUCK_QUIRK BIT_ULL(20) ++#define XHCI_MTK_HOST BIT_ULL(21) ++#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22) ++#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23) ++#define XHCI_MISSING_CAS BIT_ULL(24) + /* For controller with a broken Port Disable implementation */ +-#define XHCI_BROKEN_PORT_PED (1 << 25) +-#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26) +-#define XHCI_U2_DISABLE_WAKE (1 << 27) +-#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL (1 << 28) +-#define XHCI_SUSPEND_DELAY (1 << 30) ++#define XHCI_BROKEN_PORT_PED BIT_ULL(25) ++#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26) ++#define XHCI_U2_DISABLE_WAKE BIT_ULL(27) ++#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28) ++#define XHCI_HW_LPM_DISABLE BIT_ULL(29) ++#define XHCI_SUSPEND_DELAY BIT_ULL(30) ++#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31) + + unsigned int num_active_eps; + unsigned int limit_active_eps;