From: Ju-Zhe Zhong Date: Tue, 31 Jan 2023 12:49:46 +0000 (+0800) Subject: RISC-V: Add vxor.vv C++ API tests X-Git-Tag: basepoints/gcc-14~1609 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e37c8f209e08a851a1d2f90a93c265c1fece61bd;p=thirdparty%2Fgcc.git RISC-V: Add vxor.vv C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vxor_vv-1.C: New test. * g++.target/riscv/rvv/base/vxor_vv-2.C: New test. * g++.target/riscv/rvv/base/vxor_vv-3.C: New test. * g++.target/riscv/rvv/base/vxor_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vxor_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vxor_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vxor_vv_tumu-3.C: New test. --- diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C new file mode 100644 index 000000000000..e1128f0af418 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C new file mode 100644 index 000000000000..41bb26a2adbb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,31); +} + + +vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C new file mode 100644 index 000000000000..eb0b7d509390 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint8m1_t test___riscv_vxor(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint8m2_t test___riscv_vxor(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint8m4_t test___riscv_vxor(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint8m8_t test___riscv_vxor(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint16m1_t test___riscv_vxor(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint16m2_t test___riscv_vxor(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint16m4_t test___riscv_vxor(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint16m8_t test___riscv_vxor(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint32m1_t test___riscv_vxor(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint32m2_t test___riscv_vxor(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint32m4_t test___riscv_vxor(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint32m8_t test___riscv_vxor(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint64m1_t test___riscv_vxor(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint64m2_t test___riscv_vxor(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint64m4_t test___riscv_vxor(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint64m8_t test___riscv_vxor(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor(op1,op2,32); +} + + +vint8mf8_t test___riscv_vxor(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C new file mode 100644 index 000000000000..42bb7d88f44c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C new file mode 100644 index 000000000000..97e81c94393d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C new file mode 100644 index 000000000000..04c600e66c6a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_mu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C new file mode 100644 index 000000000000..a1221b54f2dc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C new file mode 100644 index 000000000000..4764c248f42a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C new file mode 100644 index 000000000000..ce67e4ea3a09 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C new file mode 100644 index 000000000000..e600967bad71 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C new file mode 100644 index 000000000000..290e0632223f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C new file mode 100644 index 000000000000..6db574a63030 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tum-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C new file mode 100644 index 000000000000..dee47dfd7620 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C new file mode 100644 index 000000000000..7d2e7b86ec33 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C new file mode 100644 index 000000000000..53f924e49a20 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vxor_vv_tumu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vxor_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vxor_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vxor_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vxor_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vxor_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vxor_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vxor_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vxor_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vxor_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vxor_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vxor_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vxor_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vxor_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vxor_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vxor_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vxor_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vxor_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vxor_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vxor_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vxor_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vxor_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vxor_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vxor_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vxor\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */