From: Greg Kroah-Hartman Date: Sun, 14 Feb 2021 08:18:58 +0000 (+0100) Subject: 5.10-stable patches X-Git-Tag: v5.4.99~42 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e3ba8b5e0d4b64352d15b15432eac06f366f197a;p=thirdparty%2Fkernel%2Fstable-queue.git 5.10-stable patches added patches: arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch cgroup-fix-psi-monitor-for-root-cgroup.patch dmaengine-move-channel-device_node-deletion-to-driver.patch drm-dp_mst-don-t-report-ports-connected-if-nothing-is-attached-to-them.patch drm-i915-fix-overlay-frontbuffer-tracking.patch drm-i915-tgl-make-sure-typec-fia-is-powered-up-when-initializing-it.patch gpio-ep93xx-fix-bug_on-port-f-usage.patch gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch gpio-mxs-gpio_mxs-should-not-default-to-y-unconditionally.patch revert-drm-amd-display-update-nv1x-sr-latency-values.patch revert-dts-phy-add-gpio-number-and-active-state-used-for-phy-reset.patch tmpfs-disallow-config_tmpfs_inode64-on-alpha.patch tmpfs-disallow-config_tmpfs_inode64-on-s390.patch tracing-check-length-before-giving-out-the-filter-buffer.patch tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch --- diff --git a/queue-5.10/arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch b/queue-5.10/arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch new file mode 100644 index 00000000000..1cf1d26ae22 --- /dev/null +++ b/queue-5.10/arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch @@ -0,0 +1,82 @@ +From c4295ab0b485b8bc50d2264bcae2acd06f25caaf Mon Sep 17 00:00:00 2001 +From: Julien Grall +Date: Wed, 10 Feb 2021 17:06:54 +0000 +Subject: arm/xen: Don't probe xenbus as part of an early initcall + +From: Julien Grall + +commit c4295ab0b485b8bc50d2264bcae2acd06f25caaf upstream. + +After Commit 3499ba8198cad ("xen: Fix event channel callback via +INTX/GSI"), xenbus_probe() will be called too early on Arm. This will +recent to a guest hang during boot. + +If the hang wasn't there, we would have ended up to call +xenbus_probe() twice (the second time is in xenbus_probe_initcall()). + +We don't need to initialize xenbus_probe() early for Arm guest. +Therefore, the call in xen_guest_init() is now removed. + +After this change, there is no more external caller for xenbus_probe(). +So the function is turned to a static one. Interestingly there were two +prototypes for it. + +Cc: stable@vger.kernel.org +Fixes: 3499ba8198cad ("xen: Fix event channel callback via INTX/GSI") +Reported-by: Ian Jackson +Signed-off-by: Julien Grall +Reviewed-by: David Woodhouse +Reviewed-by: Stefano Stabellini +Link: https://lore.kernel.org/r/20210210170654.5377-1-julien@xen.org +Signed-off-by: Juergen Gross +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm/xen/enlighten.c | 2 -- + drivers/xen/xenbus/xenbus.h | 1 - + drivers/xen/xenbus/xenbus_probe.c | 2 +- + include/xen/xenbus.h | 2 -- + 4 files changed, 1 insertion(+), 6 deletions(-) + +--- a/arch/arm/xen/enlighten.c ++++ b/arch/arm/xen/enlighten.c +@@ -370,8 +370,6 @@ static int __init xen_guest_init(void) + return -ENOMEM; + } + gnttab_init(); +- if (!xen_initial_domain()) +- xenbus_probe(); + + /* + * Making sure board specific code will not set up ops for +--- a/drivers/xen/xenbus/xenbus.h ++++ b/drivers/xen/xenbus/xenbus.h +@@ -115,7 +115,6 @@ int xenbus_probe_node(struct xen_bus_typ + const char *type, + const char *nodename); + int xenbus_probe_devices(struct xen_bus_type *bus); +-void xenbus_probe(void); + + void xenbus_dev_changed(const char *node, struct xen_bus_type *bus); + +--- a/drivers/xen/xenbus/xenbus_probe.c ++++ b/drivers/xen/xenbus/xenbus_probe.c +@@ -683,7 +683,7 @@ void unregister_xenstore_notifier(struct + } + EXPORT_SYMBOL_GPL(unregister_xenstore_notifier); + +-void xenbus_probe(void) ++static void xenbus_probe(void) + { + xenstored_ready = 1; + +--- a/include/xen/xenbus.h ++++ b/include/xen/xenbus.h +@@ -192,8 +192,6 @@ void xs_suspend_cancel(void); + + struct work_struct; + +-void xenbus_probe(void); +- + #define XENBUS_IS_ERR_READ(str) ({ \ + if (!IS_ERR(str) && strlen(str) == 0) { \ + kfree(str); \ diff --git a/queue-5.10/cgroup-fix-psi-monitor-for-root-cgroup.patch b/queue-5.10/cgroup-fix-psi-monitor-for-root-cgroup.patch new file mode 100644 index 00000000000..ca36a38aeb6 --- /dev/null +++ b/queue-5.10/cgroup-fix-psi-monitor-for-root-cgroup.patch @@ -0,0 +1,51 @@ +From 385aac1519417b89cb91b77c22e4ca21db563cd0 Mon Sep 17 00:00:00 2001 +From: Odin Ugedal +Date: Sat, 16 Jan 2021 18:36:33 +0100 +Subject: cgroup: fix psi monitor for root cgroup + +From: Odin Ugedal + +commit 385aac1519417b89cb91b77c22e4ca21db563cd0 upstream. + +Fix NULL pointer dereference when adding new psi monitor to the root +cgroup. PSI files for root cgroup was introduced in df5ba5be742 by using +system wide psi struct when reading, but file write/monitor was not +properly fixed. Since the PSI config for the root cgroup isn't +initialized, the current implementation tries to lock a NULL ptr, +resulting in a crash. + +Can be triggered by running this as root: +$ tee /sys/fs/cgroup/cpu.pressure <<< "some 10000 1000000" + +Signed-off-by: Odin Ugedal +Reviewed-by: Suren Baghdasaryan +Acked-by: Dan Schatzberg +Fixes: df5ba5be7425 ("kernel/sched/psi.c: expose pressure metrics on root cgroup") +Acked-by: Johannes Weiner +Cc: stable@vger.kernel.org # 5.2+ +Signed-off-by: Tejun Heo +Signed-off-by: Greg Kroah-Hartman +--- + kernel/cgroup/cgroup.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/kernel/cgroup/cgroup.c ++++ b/kernel/cgroup/cgroup.c +@@ -3567,6 +3567,7 @@ static ssize_t cgroup_pressure_write(str + { + struct psi_trigger *new; + struct cgroup *cgrp; ++ struct psi_group *psi; + + cgrp = cgroup_kn_lock_live(of->kn, false); + if (!cgrp) +@@ -3575,7 +3576,8 @@ static ssize_t cgroup_pressure_write(str + cgroup_get(cgrp); + cgroup_kn_unlock(of->kn); + +- new = psi_trigger_create(&cgrp->psi, buf, nbytes, res); ++ psi = cgroup_ino(cgrp) == 1 ? &psi_system : &cgrp->psi; ++ new = psi_trigger_create(psi, buf, nbytes, res); + if (IS_ERR(new)) { + cgroup_put(cgrp); + return PTR_ERR(new); diff --git a/queue-5.10/dmaengine-move-channel-device_node-deletion-to-driver.patch b/queue-5.10/dmaengine-move-channel-device_node-deletion-to-driver.patch new file mode 100644 index 00000000000..73f7aa2ca23 --- /dev/null +++ b/queue-5.10/dmaengine-move-channel-device_node-deletion-to-driver.patch @@ -0,0 +1,66 @@ +From e594443196d6e0ef3d3b30320c49b3a4d4f9a547 Mon Sep 17 00:00:00 2001 +From: Dave Jiang +Date: Mon, 18 Jan 2021 10:28:44 -0700 +Subject: dmaengine: move channel device_node deletion to driver + +From: Dave Jiang + +commit e594443196d6e0ef3d3b30320c49b3a4d4f9a547 upstream. + +Channel device_node deletion is managed by the device driver rather than +the dmaengine core. The deletion was accidentally introduced when making +channel unregister dynamic. It causes xilinx_dma module to crash on unload +as reported by Radhey. Remove chan->device_node delete in dmaengine and +also fix up idxd driver. + +[ 42.142705] Internal error: Oops: 96000044 [#1] SMP +[ 42.147566] Modules linked in: xilinx_dma(-) clk_xlnx_clock_wizard uio_pdrv_genirq +[ 42.155139] CPU: 1 PID: 2075 Comm: rmmod Not tainted 5.10.1-00026-g3a2e6dd7a05-dirty #192 +[ 42.163302] Hardware name: Enclustra XU5 SOM (DT) +[ 42.167992] pstate: 40000005 (nZcv daif -PAN -UAO -TCO BTYPE=--) +[ 42.173996] pc : xilinx_dma_chan_remove+0x74/0xa0 [xilinx_dma] +[ 42.179815] lr : xilinx_dma_chan_remove+0x70/0xa0 [xilinx_dma] +[ 42.185636] sp : ffffffc01112bca0 +[ 42.188935] x29: ffffffc01112bca0 x28: ffffff80402ea640 + +xilinx_dma_chan_remove+0x74/0xa0: +__list_del at ./include/linux/list.h:112 (inlined by) +__list_del_entry at./include/linux/list.h:135 (inlined by) +list_del at ./include/linux/list.h:146 (inlined by) +xilinx_dma_chan_remove at drivers/dma/xilinx/xilinx_dma.c:2546 + +Fixes: e81274cd6b52 ("dmaengine: add support to dynamic register/unregister of channels") +Reported-by: Radhey Shyam Pandey +Signed-off-by: Dave Jiang +Tested-by: Radhey Shyam Pandey +Link: https://lore.kernel.org/r/161099092469.2495902.5064826526660062342.stgit@djiang5-desk3.ch.intel.com +Signed-off-by: Vinod Koul +Cc: stable@vger.kernel.org # 5.9+ +Signed-off-by: Greg Kroah-Hartman +--- + drivers/dma/dmaengine.c | 1 - + drivers/dma/idxd/dma.c | 5 ++++- + 2 files changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/dma/dmaengine.c ++++ b/drivers/dma/dmaengine.c +@@ -1110,7 +1110,6 @@ static void __dma_async_device_channel_u + "%s called while %d clients hold a reference\n", + __func__, chan->client_count); + mutex_lock(&dma_list_mutex); +- list_del(&chan->device_node); + device->chancnt--; + chan->dev->chan = NULL; + mutex_unlock(&dma_list_mutex); +--- a/drivers/dma/idxd/dma.c ++++ b/drivers/dma/idxd/dma.c +@@ -214,5 +214,8 @@ int idxd_register_dma_channel(struct idx + + void idxd_unregister_dma_channel(struct idxd_wq *wq) + { +- dma_async_device_channel_unregister(&wq->idxd->dma_dev, &wq->dma_chan); ++ struct dma_chan *chan = &wq->dma_chan; ++ ++ dma_async_device_channel_unregister(&wq->idxd->dma_dev, chan); ++ list_del(&chan->device_node); + } diff --git a/queue-5.10/drm-dp_mst-don-t-report-ports-connected-if-nothing-is-attached-to-them.patch b/queue-5.10/drm-dp_mst-don-t-report-ports-connected-if-nothing-is-attached-to-them.patch new file mode 100644 index 00000000000..3158c613a25 --- /dev/null +++ b/queue-5.10/drm-dp_mst-don-t-report-ports-connected-if-nothing-is-attached-to-them.patch @@ -0,0 +1,42 @@ +From 873e5bb9fbd99e4a26c448b5c7af942a6d7aa60d Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Mon, 1 Feb 2021 14:01:42 +0200 +Subject: drm/dp_mst: Don't report ports connected if nothing is attached to them + +From: Imre Deak + +commit 873e5bb9fbd99e4a26c448b5c7af942a6d7aa60d upstream. + +Reporting a port as connected if nothing is attached to them leads to +any i2c transactions on this port trying to use an uninitialized i2c +adapter, fix this. + +Let's account for this case even if branch devices have no good reason +to report a port as plugged with their peer device type set to 'none'. + +Fixes: db1a07956968 ("drm/dp_mst: Handle SST-only branch device case") +References: https://gitlab.freedesktop.org/drm/intel/-/issues/2987 +References: https://gitlab.freedesktop.org/drm/intel/-/issues/1963 +Cc: Wayne Lin +Cc: Lyude Paul +Cc: # v5.5+ +Cc: intel-gfx@lists.freedesktop.org +Signed-off-by: Imre Deak +Reviewed-by: Lyude Paul +Reported-by: Thiago Macieira +Link: https://patchwork.freedesktop.org/patch/msgid/20210201120145.350258-1-imre.deak@intel.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/drm_dp_mst_topology.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/drm_dp_mst_topology.c ++++ b/drivers/gpu/drm/drm_dp_mst_topology.c +@@ -4224,6 +4224,7 @@ drm_dp_mst_detect_port(struct drm_connec + + switch (port->pdt) { + case DP_PEER_DEVICE_NONE: ++ break; + case DP_PEER_DEVICE_MST_BRANCHING: + if (!port->mcs) + ret = connector_status_connected; diff --git a/queue-5.10/drm-i915-fix-overlay-frontbuffer-tracking.patch b/queue-5.10/drm-i915-fix-overlay-frontbuffer-tracking.patch new file mode 100644 index 00000000000..b71352aee72 --- /dev/null +++ b/queue-5.10/drm-i915-fix-overlay-frontbuffer-tracking.patch @@ -0,0 +1,77 @@ +From 5feba0e905c495a217aea9db4ea91093d8fe5dde Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Tue, 9 Feb 2021 04:19:17 +0200 +Subject: drm/i915: Fix overlay frontbuffer tracking +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 5feba0e905c495a217aea9db4ea91093d8fe5dde upstream. + +We don't have a persistent fb holding a reference to the frontbuffer +object, so every time we do the get+put we throw the frontbuffer object +immediately away. And so the next time around we get a pristine +frontbuffer object with bits==0 even for the old vma. This confuses +the frontbuffer tracking code which understandably expects the old +frontbuffer to have the overlay's bit set. + +Fix this by hanging on to the frontbuffer reference until the next +flip. And just to make this a bit more clear let's track the frontbuffer +explicitly instead of just grabbing it via the old vma. + +Cc: stable@vger.kernel.org +Cc: Chris Wilson +Cc: Joonas Lahtinen +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1136 +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20210209021918.16234-2-ville.syrjala@linux.intel.com +Fixes: 8e7cb1799b4f ("drm/i915: Extract intel_frontbuffer active tracking") +Reviewed-by: Chris Wilson +(cherry picked from commit 553c23bdb4775130f333f07a51b047276bc53f79) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_overlay.c | 17 ++++++++--------- + 1 file changed, 8 insertions(+), 9 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_overlay.c ++++ b/drivers/gpu/drm/i915/display/intel_overlay.c +@@ -182,6 +182,7 @@ struct intel_overlay { + struct intel_crtc *crtc; + struct i915_vma *vma; + struct i915_vma *old_vma; ++ struct intel_frontbuffer *frontbuffer; + bool active; + bool pfit_active; + u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ +@@ -282,21 +283,19 @@ static void intel_overlay_flip_prepare(s + struct i915_vma *vma) + { + enum pipe pipe = overlay->crtc->pipe; +- struct intel_frontbuffer *from = NULL, *to = NULL; ++ struct intel_frontbuffer *frontbuffer = NULL; + + drm_WARN_ON(&overlay->i915->drm, overlay->old_vma); + +- if (overlay->vma) +- from = intel_frontbuffer_get(overlay->vma->obj); + if (vma) +- to = intel_frontbuffer_get(vma->obj); ++ frontbuffer = intel_frontbuffer_get(vma->obj); + +- intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe)); ++ intel_frontbuffer_track(overlay->frontbuffer, frontbuffer, ++ INTEL_FRONTBUFFER_OVERLAY(pipe)); + +- if (to) +- intel_frontbuffer_put(to); +- if (from) +- intel_frontbuffer_put(from); ++ if (overlay->frontbuffer) ++ intel_frontbuffer_put(overlay->frontbuffer); ++ overlay->frontbuffer = frontbuffer; + + intel_frontbuffer_flip_prepare(overlay->i915, + INTEL_FRONTBUFFER_OVERLAY(pipe)); diff --git a/queue-5.10/drm-i915-tgl-make-sure-typec-fia-is-powered-up-when-initializing-it.patch b/queue-5.10/drm-i915-tgl-make-sure-typec-fia-is-powered-up-when-initializing-it.patch new file mode 100644 index 00000000000..e13d91f71a4 --- /dev/null +++ b/queue-5.10/drm-i915-tgl-make-sure-typec-fia-is-powered-up-when-initializing-it.patch @@ -0,0 +1,117 @@ +From 2f51312bebb77962a518b4c6de777dd378b6110a Mon Sep 17 00:00:00 2001 +From: Imre Deak +Date: Mon, 8 Feb 2021 17:43:03 +0200 +Subject: drm/i915/tgl+: Make sure TypeC FIA is powered up when initializing it +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Imre Deak + +commit 2f51312bebb77962a518b4c6de777dd378b6110a upstream. + +The TypeC FIA can be powered down if the TC-COLD power state is allowed, +so block the TC-COLD state when initializing the FIA. + +Note that this isn't needed on ICL where the FIA is never modular and +which has no generic way to block TC-COLD (except for platforms with a +legacy TypeC port and on those too only via these legacy ports, not via +a DP-alt/TBT port). + +Cc: # v5.10+ +Cc: José Roberto de Souza +Reported-by: Paul Menzel +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3027 +Signed-off-by: Imre Deak +Link: https://patchwork.freedesktop.org/patch/msgid/20210208154303.6839-1-imre.deak@intel.com +Reviewed-by: Jos� Roberto de Souza +(cherry picked from commit f48993e5d26b079e8c80fff002499a213dbdb1b4) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_tc.c | 67 +++++++++++++++++--------------- + 1 file changed, 37 insertions(+), 30 deletions(-) + +--- a/drivers/gpu/drm/i915/display/intel_tc.c ++++ b/drivers/gpu/drm/i915/display/intel_tc.c +@@ -23,36 +23,6 @@ static const char *tc_port_mode_name(enu + return names[mode]; + } + +-static void +-tc_port_load_fia_params(struct drm_i915_private *i915, +- struct intel_digital_port *dig_port) +-{ +- enum port port = dig_port->base.port; +- enum tc_port tc_port = intel_port_to_tc(i915, port); +- u32 modular_fia; +- +- if (INTEL_INFO(i915)->display.has_modular_fia) { +- modular_fia = intel_uncore_read(&i915->uncore, +- PORT_TX_DFLEXDPSP(FIA1)); +- drm_WARN_ON(&i915->drm, modular_fia == 0xffffffff); +- modular_fia &= MODULAR_FIA_MASK; +- } else { +- modular_fia = 0; +- } +- +- /* +- * Each Modular FIA instance houses 2 TC ports. In SOC that has more +- * than two TC ports, there are multiple instances of Modular FIA. +- */ +- if (modular_fia) { +- dig_port->tc_phy_fia = tc_port / 2; +- dig_port->tc_phy_fia_idx = tc_port % 2; +- } else { +- dig_port->tc_phy_fia = FIA1; +- dig_port->tc_phy_fia_idx = tc_port; +- } +-} +- + static enum intel_display_power_domain + tc_cold_get_power_domain(struct intel_digital_port *dig_port) + { +@@ -646,6 +616,43 @@ void intel_tc_port_put_link(struct intel + mutex_unlock(&dig_port->tc_lock); + } + ++static bool ++tc_has_modular_fia(struct drm_i915_private *i915, struct intel_digital_port *dig_port) ++{ ++ intel_wakeref_t wakeref; ++ u32 val; ++ ++ if (!INTEL_INFO(i915)->display.has_modular_fia) ++ return false; ++ ++ wakeref = tc_cold_block(dig_port); ++ val = intel_uncore_read(&i915->uncore, PORT_TX_DFLEXDPSP(FIA1)); ++ tc_cold_unblock(dig_port, wakeref); ++ ++ drm_WARN_ON(&i915->drm, val == 0xffffffff); ++ ++ return val & MODULAR_FIA_MASK; ++} ++ ++static void ++tc_port_load_fia_params(struct drm_i915_private *i915, struct intel_digital_port *dig_port) ++{ ++ enum port port = dig_port->base.port; ++ enum tc_port tc_port = intel_port_to_tc(i915, port); ++ ++ /* ++ * Each Modular FIA instance houses 2 TC ports. In SOC that has more ++ * than two TC ports, there are multiple instances of Modular FIA. ++ */ ++ if (tc_has_modular_fia(i915, dig_port)) { ++ dig_port->tc_phy_fia = tc_port / 2; ++ dig_port->tc_phy_fia_idx = tc_port % 2; ++ } else { ++ dig_port->tc_phy_fia = FIA1; ++ dig_port->tc_phy_fia_idx = tc_port; ++ } ++} ++ + void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy) + { + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); diff --git a/queue-5.10/gpio-ep93xx-fix-bug_on-port-f-usage.patch b/queue-5.10/gpio-ep93xx-fix-bug_on-port-f-usage.patch new file mode 100644 index 00000000000..72cd4fc2b49 --- /dev/null +++ b/queue-5.10/gpio-ep93xx-fix-bug_on-port-f-usage.patch @@ -0,0 +1,399 @@ +From 8b81a7ab8055d01d827ef66374b126eeac3bd108 Mon Sep 17 00:00:00 2001 +From: Nikita Shubin +Date: Tue, 9 Feb 2021 16:31:04 +0300 +Subject: gpio: ep93xx: fix BUG_ON port F usage + +From: Nikita Shubin + +commit 8b81a7ab8055d01d827ef66374b126eeac3bd108 upstream. + +Two index spaces and ep93xx_gpio_port are confusing. + +Instead add a separate struct to store necessary data and remove +ep93xx_gpio_port. + +- add struct to store IRQ related data for each IRQ capable chip +- replace offset array with defined offsets +- add IRQ registers offset for each IRQ capable chip into + ep93xx_gpio_banks + +------------[ cut here ]------------ +kernel BUG at drivers/gpio/gpio-ep93xx.c:64! +---[ end trace 3f6544e133e9f5ae ]--- + +Fixes: fd935fc421e74 ("gpio: ep93xx: Do not pingpong irq numbers") +Cc: +Reviewed-by: Alexander Sverdlin +Tested-by: Alexander Sverdlin +Signed-off-by: Nikita Shubin +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpio/gpio-ep93xx.c | 186 +++++++++++++++++++++++---------------------- + 1 file changed, 99 insertions(+), 87 deletions(-) + +--- a/drivers/gpio/gpio-ep93xx.c ++++ b/drivers/gpio/gpio-ep93xx.c +@@ -25,6 +25,9 @@ + /* Maximum value for gpio line identifiers */ + #define EP93XX_GPIO_LINE_MAX 63 + ++/* Number of GPIO chips in EP93XX */ ++#define EP93XX_GPIO_CHIP_NUM 8 ++ + /* Maximum value for irq capable line identifiers */ + #define EP93XX_GPIO_LINE_MAX_IRQ 23 + +@@ -34,74 +37,74 @@ + */ + #define EP93XX_GPIO_F_IRQ_BASE 80 + ++struct ep93xx_gpio_irq_chip { ++ u8 irq_offset; ++ u8 int_unmasked; ++ u8 int_enabled; ++ u8 int_type1; ++ u8 int_type2; ++ u8 int_debounce; ++}; ++ ++struct ep93xx_gpio_chip { ++ struct gpio_chip gc; ++ struct ep93xx_gpio_irq_chip *eic; ++}; ++ + struct ep93xx_gpio { + void __iomem *base; +- struct gpio_chip gc[8]; ++ struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM]; + }; + +-/************************************************************************* +- * Interrupt handling for EP93xx on-chip GPIOs +- *************************************************************************/ +-static unsigned char gpio_int_unmasked[3]; +-static unsigned char gpio_int_enabled[3]; +-static unsigned char gpio_int_type1[3]; +-static unsigned char gpio_int_type2[3]; +-static unsigned char gpio_int_debounce[3]; ++#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc) + +-/* Port ordering is: A B F */ +-static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; +-static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; +-static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; +-static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; +-static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; +- +-static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port) ++static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc) + { +- BUG_ON(port > 2); +- +- writeb_relaxed(0, epg->base + int_en_register_offset[port]); ++ struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc); + +- writeb_relaxed(gpio_int_type2[port], +- epg->base + int_type2_register_offset[port]); +- +- writeb_relaxed(gpio_int_type1[port], +- epg->base + int_type1_register_offset[port]); +- +- writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], +- epg->base + int_en_register_offset[port]); ++ return egc->eic; + } + +-static int ep93xx_gpio_port(struct gpio_chip *gc) +-{ +- struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = 0; ++/************************************************************************* ++ * Interrupt handling for EP93xx on-chip GPIOs ++ *************************************************************************/ ++#define EP93XX_INT_TYPE1_OFFSET 0x00 ++#define EP93XX_INT_TYPE2_OFFSET 0x04 ++#define EP93XX_INT_EOI_OFFSET 0x08 ++#define EP93XX_INT_EN_OFFSET 0x0c ++#define EP93XX_INT_STATUS_OFFSET 0x10 ++#define EP93XX_INT_RAW_STATUS_OFFSET 0x14 ++#define EP93XX_INT_DEBOUNCE_OFFSET 0x18 ++ ++static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, ++ struct ep93xx_gpio_irq_chip *eic) ++{ ++ writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + +- while (port < ARRAY_SIZE(epg->gc) && gc != &epg->gc[port]) +- port++; ++ writeb_relaxed(eic->int_type2, ++ epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET); + +- /* This should not happen but is there as a last safeguard */ +- if (port == ARRAY_SIZE(epg->gc)) { +- pr_crit("can't find the GPIO port\n"); +- return 0; +- } ++ writeb_relaxed(eic->int_type1, ++ epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET); + +- return port; ++ writeb_relaxed(eic->int_unmasked & eic->int_enabled, ++ epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET); + } + + static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, + unsigned int offset, bool enable) + { + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + int port_mask = BIT(offset); + + if (enable) +- gpio_int_debounce[port] |= port_mask; ++ eic->int_debounce |= port_mask; + else +- gpio_int_debounce[port] &= ~port_mask; ++ eic->int_debounce &= ~port_mask; + +- writeb(gpio_int_debounce[port], +- epg->base + int_debounce_register_offset[port]); ++ writeb(eic->int_debounce, ++ epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET); + } + + static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) +@@ -122,12 +125,12 @@ static void ep93xx_gpio_ab_irq_handler(s + */ + stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS); + for_each_set_bit(offset, &stat, 8) +- generic_handle_irq(irq_find_mapping(epg->gc[0].irq.domain, ++ generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain, + offset)); + + stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS); + for_each_set_bit(offset, &stat, 8) +- generic_handle_irq(irq_find_mapping(epg->gc[1].irq.domain, ++ generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain, + offset)); + + chained_irq_exit(irqchip, desc); +@@ -153,52 +156,52 @@ static void ep93xx_gpio_f_irq_handler(st + static void ep93xx_gpio_irq_ack(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + int port_mask = BIT(d->irq & 7); + + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { +- gpio_int_type2[port] ^= port_mask; /* switch edge direction */ +- ep93xx_gpio_update_int_params(epg, port); ++ eic->int_type2 ^= port_mask; /* switch edge direction */ ++ ep93xx_gpio_update_int_params(epg, eic); + } + +- writeb(port_mask, epg->base + eoi_register_offset[port]); ++ writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + } + + static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + int port_mask = BIT(d->irq & 7); + + if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) +- gpio_int_type2[port] ^= port_mask; /* switch edge direction */ ++ eic->int_type2 ^= port_mask; /* switch edge direction */ + +- gpio_int_unmasked[port] &= ~port_mask; +- ep93xx_gpio_update_int_params(epg, port); ++ eic->int_unmasked &= ~port_mask; ++ ep93xx_gpio_update_int_params(epg, eic); + +- writeb(port_mask, epg->base + eoi_register_offset[port]); ++ writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET); + } + + static void ep93xx_gpio_irq_mask(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + +- gpio_int_unmasked[port] &= ~BIT(d->irq & 7); +- ep93xx_gpio_update_int_params(epg, port); ++ eic->int_unmasked &= ~BIT(d->irq & 7); ++ ep93xx_gpio_update_int_params(epg, eic); + } + + static void ep93xx_gpio_irq_unmask(struct irq_data *d) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + +- gpio_int_unmasked[port] |= BIT(d->irq & 7); +- ep93xx_gpio_update_int_params(epg, port); ++ eic->int_unmasked |= BIT(d->irq & 7); ++ ep93xx_gpio_update_int_params(epg, eic); + } + + /* +@@ -209,8 +212,8 @@ static void ep93xx_gpio_irq_unmask(struc + static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) + { + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); ++ struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); +- int port = ep93xx_gpio_port(gc); + int offset = d->irq & 7; + int port_mask = BIT(offset); + irq_flow_handler_t handler; +@@ -219,32 +222,32 @@ static int ep93xx_gpio_irq_type(struct i + + switch (type) { + case IRQ_TYPE_EDGE_RISING: +- gpio_int_type1[port] |= port_mask; +- gpio_int_type2[port] |= port_mask; ++ eic->int_type1 |= port_mask; ++ eic->int_type2 |= port_mask; + handler = handle_edge_irq; + break; + case IRQ_TYPE_EDGE_FALLING: +- gpio_int_type1[port] |= port_mask; +- gpio_int_type2[port] &= ~port_mask; ++ eic->int_type1 |= port_mask; ++ eic->int_type2 &= ~port_mask; + handler = handle_edge_irq; + break; + case IRQ_TYPE_LEVEL_HIGH: +- gpio_int_type1[port] &= ~port_mask; +- gpio_int_type2[port] |= port_mask; ++ eic->int_type1 &= ~port_mask; ++ eic->int_type2 |= port_mask; + handler = handle_level_irq; + break; + case IRQ_TYPE_LEVEL_LOW: +- gpio_int_type1[port] &= ~port_mask; +- gpio_int_type2[port] &= ~port_mask; ++ eic->int_type1 &= ~port_mask; ++ eic->int_type2 &= ~port_mask; + handler = handle_level_irq; + break; + case IRQ_TYPE_EDGE_BOTH: +- gpio_int_type1[port] |= port_mask; ++ eic->int_type1 |= port_mask; + /* set initial polarity based on current input level */ + if (gc->get(gc, offset)) +- gpio_int_type2[port] &= ~port_mask; /* falling */ ++ eic->int_type2 &= ~port_mask; /* falling */ + else +- gpio_int_type2[port] |= port_mask; /* rising */ ++ eic->int_type2 |= port_mask; /* rising */ + handler = handle_edge_irq; + break; + default: +@@ -253,9 +256,9 @@ static int ep93xx_gpio_irq_type(struct i + + irq_set_handler_locked(d, handler); + +- gpio_int_enabled[port] |= port_mask; ++ eic->int_enabled |= port_mask; + +- ep93xx_gpio_update_int_params(epg, port); ++ ep93xx_gpio_update_int_params(epg, eic); + + return 0; + } +@@ -276,17 +279,19 @@ struct ep93xx_gpio_bank { + const char *label; + int data; + int dir; ++ int irq; + int base; + bool has_irq; + bool has_hierarchical_irq; + unsigned int irq_base; + }; + +-#define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _has_irq, _has_hier, _irq_base) \ ++#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \ + { \ + .label = _label, \ + .data = _data, \ + .dir = _dir, \ ++ .irq = _irq, \ + .base = _base, \ + .has_irq = _has_irq, \ + .has_hierarchical_irq = _has_hier, \ +@@ -295,16 +300,16 @@ struct ep93xx_gpio_bank { + + static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { + /* Bank A has 8 IRQs */ +- EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true, false, 64), ++ EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64), + /* Bank B has 8 IRQs */ +- EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true, false, 72), +- EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false, false, 0), +- EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false, false, 0), +- EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false, false, 0), ++ EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72), ++ EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0), ++ EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0), ++ EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0), + /* Bank F has 8 IRQs */ +- EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, false, true, 0), +- EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false, false, 0), +- EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false, false, 0), ++ EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0), ++ EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0), ++ EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0), + }; + + static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, +@@ -326,13 +331,14 @@ static int ep93xx_gpio_f_to_irq(struct g + return EP93XX_GPIO_F_IRQ_BASE + offset; + } + +-static int ep93xx_gpio_add_bank(struct gpio_chip *gc, ++static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, + struct platform_device *pdev, + struct ep93xx_gpio *epg, + struct ep93xx_gpio_bank *bank) + { + void __iomem *data = epg->base + bank->data; + void __iomem *dir = epg->base + bank->dir; ++ struct gpio_chip *gc = &egc->gc; + struct device *dev = &pdev->dev; + struct gpio_irq_chip *girq; + int err; +@@ -347,6 +353,12 @@ static int ep93xx_gpio_add_bank(struct g + girq = &gc->irq; + if (bank->has_irq || bank->has_hierarchical_irq) { + gc->set_config = ep93xx_gpio_set_config; ++ egc->eic = devm_kcalloc(dev, 1, ++ sizeof(*egc->eic), ++ GFP_KERNEL); ++ if (!egc->eic) ++ return -ENOMEM; ++ egc->eic->irq_offset = bank->irq; + girq->chip = &ep93xx_gpio_irq_chip; + } + +@@ -415,7 +427,7 @@ static int ep93xx_gpio_probe(struct plat + return PTR_ERR(epg->base); + + for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { +- struct gpio_chip *gc = &epg->gc[i]; ++ struct ep93xx_gpio_chip *gc = &epg->gc[i]; + struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; + + if (ep93xx_gpio_add_bank(gc, pdev, epg, bank)) diff --git a/queue-5.10/gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch b/queue-5.10/gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch new file mode 100644 index 00000000000..3d927c3a99b --- /dev/null +++ b/queue-5.10/gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch @@ -0,0 +1,102 @@ +From 28dc10eb77a2db7681b08e3b109764bbe469e347 Mon Sep 17 00:00:00 2001 +From: Nikita Shubin +Date: Tue, 9 Feb 2021 16:31:05 +0300 +Subject: gpio: ep93xx: Fix single irqchip with multi gpiochips + +From: Nikita Shubin + +commit 28dc10eb77a2db7681b08e3b109764bbe469e347 upstream. + +Fixes the following warnings which results in interrupts disabled on +port B/F: + +gpio gpiochip1: (B): detected irqchip that is shared with multiple gpiochips: please fix the driver. +gpio gpiochip5: (F): detected irqchip that is shared with multiple gpiochips: please fix the driver. + +- added separate irqchip for each interrupt capable gpiochip +- provided unique names for each irqchip + +Fixes: d2b091961510 ("gpio: ep93xx: Pass irqchip when adding gpiochip") +Cc: +Signed-off-by: Nikita Shubin +Tested-by: Alexander Sverdlin +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpio/gpio-ep93xx.c | 30 +++++++++++++++++++----------- + 1 file changed, 19 insertions(+), 11 deletions(-) + +--- a/drivers/gpio/gpio-ep93xx.c ++++ b/drivers/gpio/gpio-ep93xx.c +@@ -38,6 +38,7 @@ + #define EP93XX_GPIO_F_IRQ_BASE 80 + + struct ep93xx_gpio_irq_chip { ++ struct irq_chip ic; + u8 irq_offset; + u8 int_unmasked; + u8 int_enabled; +@@ -263,15 +264,6 @@ static int ep93xx_gpio_irq_type(struct i + return 0; + } + +-static struct irq_chip ep93xx_gpio_irq_chip = { +- .name = "GPIO", +- .irq_ack = ep93xx_gpio_irq_ack, +- .irq_mask_ack = ep93xx_gpio_irq_mask_ack, +- .irq_mask = ep93xx_gpio_irq_mask, +- .irq_unmask = ep93xx_gpio_irq_unmask, +- .irq_set_type = ep93xx_gpio_irq_type, +-}; +- + /************************************************************************* + * gpiolib interface for EP93xx on-chip GPIOs + *************************************************************************/ +@@ -331,6 +323,15 @@ static int ep93xx_gpio_f_to_irq(struct g + return EP93XX_GPIO_F_IRQ_BASE + offset; + } + ++static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic) ++{ ++ ic->irq_ack = ep93xx_gpio_irq_ack; ++ ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack; ++ ic->irq_mask = ep93xx_gpio_irq_mask; ++ ic->irq_unmask = ep93xx_gpio_irq_unmask; ++ ic->irq_set_type = ep93xx_gpio_irq_type; ++} ++ + static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc, + struct platform_device *pdev, + struct ep93xx_gpio *epg, +@@ -352,6 +353,8 @@ static int ep93xx_gpio_add_bank(struct e + + girq = &gc->irq; + if (bank->has_irq || bank->has_hierarchical_irq) { ++ struct irq_chip *ic; ++ + gc->set_config = ep93xx_gpio_set_config; + egc->eic = devm_kcalloc(dev, 1, + sizeof(*egc->eic), +@@ -359,7 +362,12 @@ static int ep93xx_gpio_add_bank(struct e + if (!egc->eic) + return -ENOMEM; + egc->eic->irq_offset = bank->irq; +- girq->chip = &ep93xx_gpio_irq_chip; ++ ic = &egc->eic->ic; ++ ic->name = devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label); ++ if (!ic->name) ++ return -ENOMEM; ++ ep93xx_init_irq_chip(dev, ic); ++ girq->chip = ic; + } + + if (bank->has_irq) { +@@ -401,7 +409,7 @@ static int ep93xx_gpio_add_bank(struct e + gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i; + irq_set_chip_data(gpio_irq, &epg->gc[5]); + irq_set_chip_and_handler(gpio_irq, +- &ep93xx_gpio_irq_chip, ++ girq->chip, + handle_level_irq); + irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); + } diff --git a/queue-5.10/gpio-mxs-gpio_mxs-should-not-default-to-y-unconditionally.patch b/queue-5.10/gpio-mxs-gpio_mxs-should-not-default-to-y-unconditionally.patch new file mode 100644 index 00000000000..5f9f8a8b12d --- /dev/null +++ b/queue-5.10/gpio-mxs-gpio_mxs-should-not-default-to-y-unconditionally.patch @@ -0,0 +1,35 @@ +From 97c6e28d388a5000d780d2a63c32f422827f5aa3 Mon Sep 17 00:00:00 2001 +From: Geert Uytterhoeven +Date: Mon, 8 Feb 2021 15:51:53 +0100 +Subject: gpio: mxs: GPIO_MXS should not default to y unconditionally + +From: Geert Uytterhoeven + +commit 97c6e28d388a5000d780d2a63c32f422827f5aa3 upstream. + +Merely enabling CONFIG_COMPILE_TEST should not enable additional code. +To fix this, restrict the automatic enabling of GPIO_MXS to ARCH_MXS, +and ask the user in case of compile-testing. + +Fixes: 6876ca311bfca5d7 ("gpio: mxs: add COMPILE_TEST support for GPIO_MXS") +Cc: +Signed-off-by: Geert Uytterhoeven +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpio/Kconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpio/Kconfig ++++ b/drivers/gpio/Kconfig +@@ -428,8 +428,9 @@ config GPIO_MXC + select GENERIC_IRQ_CHIP + + config GPIO_MXS +- def_bool y ++ bool "Freescale MXS GPIO support" if COMPILE_TEST + depends on ARCH_MXS || COMPILE_TEST ++ default y if ARCH_MXS + select GPIO_GENERIC + select GENERIC_IRQ_CHIP + diff --git a/queue-5.10/revert-drm-amd-display-update-nv1x-sr-latency-values.patch b/queue-5.10/revert-drm-amd-display-update-nv1x-sr-latency-values.patch new file mode 100644 index 00000000000..1549f4b70b4 --- /dev/null +++ b/queue-5.10/revert-drm-amd-display-update-nv1x-sr-latency-values.patch @@ -0,0 +1,38 @@ +From cf050f96e0970a557601953ed7269d07a7885078 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Wed, 3 Feb 2021 14:03:50 -0500 +Subject: Revert "drm/amd/display: Update NV1x SR latency values" + +From: Alex Deucher + +commit cf050f96e0970a557601953ed7269d07a7885078 upstream. + +This reverts commit 4a3dea8932d3b1199680d2056dd91d31d94d70b7. + +This causes blank screens for some users. + +Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1482 +Cc: Alvin Lee +Cc: Jun Lei +Cc: Rodrigo Siqueira +Reviewed-by: Rodrigo Siqueira +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +@@ -297,8 +297,8 @@ static struct _vcs_dpi_soc_bounding_box_ + }, + }, + .num_states = 5, +- .sr_exit_time_us = 11.6, +- .sr_enter_plus_exit_time_us = 13.9, ++ .sr_exit_time_us = 8.6, ++ .sr_enter_plus_exit_time_us = 10.9, + .urgent_latency_us = 4.0, + .urgent_latency_pixel_data_only_us = 4.0, + .urgent_latency_pixel_mixed_with_vm_data_us = 4.0, diff --git a/queue-5.10/revert-dts-phy-add-gpio-number-and-active-state-used-for-phy-reset.patch b/queue-5.10/revert-dts-phy-add-gpio-number-and-active-state-used-for-phy-reset.patch new file mode 100644 index 00000000000..7c683d54a45 --- /dev/null +++ b/queue-5.10/revert-dts-phy-add-gpio-number-and-active-state-used-for-phy-reset.patch @@ -0,0 +1,36 @@ +From 3da3cc1b5f47115b16b5ffeeb4bf09ec331b0164 Mon Sep 17 00:00:00 2001 +From: Palmer Dabbelt +Date: Thu, 4 Feb 2021 19:41:12 -0800 +Subject: Revert "dts: phy: add GPIO number and active state used for phy reset" + +From: Palmer Dabbelt + +commit 3da3cc1b5f47115b16b5ffeeb4bf09ec331b0164 upstream. + +VSC8541 phys need a special reset sequence, which the driver doesn't +currentlny support. As a result enabling the reset via GPIO essentially +guarnteees that the device won't work correctly. We've been relying on +bootloaders to reset the device for years, with this revert we'll go +back to doing so until we can sort out how to get the reset sequence +into the kernel. + +This reverts commit a0fa9d727043da2238432471e85de0bdb8a8df65. + +Fixes: a0fa9d727043 ("dts: phy: add GPIO number and active state used for phy reset") +Cc: stable@vger.kernel.org +Signed-off-by: Palmer Dabbelt +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts ++++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts +@@ -90,7 +90,6 @@ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.0771"; + reg = <0>; +- reset-gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + }; + }; + diff --git a/queue-5.10/series b/queue-5.10/series index c6022b04f40..fb07a211bac 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -1 +1,16 @@ objtool-fix-seg-fault-with-clang-non-section-symbols.patch +revert-dts-phy-add-gpio-number-and-active-state-used-for-phy-reset.patch +gpio-mxs-gpio_mxs-should-not-default-to-y-unconditionally.patch +gpio-ep93xx-fix-bug_on-port-f-usage.patch +gpio-ep93xx-fix-single-irqchip-with-multi-gpiochips.patch +tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch +tracing-check-length-before-giving-out-the-filter-buffer.patch +drm-i915-fix-overlay-frontbuffer-tracking.patch +arm-xen-don-t-probe-xenbus-as-part-of-an-early-initcall.patch +cgroup-fix-psi-monitor-for-root-cgroup.patch +revert-drm-amd-display-update-nv1x-sr-latency-values.patch +drm-i915-tgl-make-sure-typec-fia-is-powered-up-when-initializing-it.patch +drm-dp_mst-don-t-report-ports-connected-if-nothing-is-attached-to-them.patch +dmaengine-move-channel-device_node-deletion-to-driver.patch +tmpfs-disallow-config_tmpfs_inode64-on-s390.patch +tmpfs-disallow-config_tmpfs_inode64-on-alpha.patch diff --git a/queue-5.10/tmpfs-disallow-config_tmpfs_inode64-on-alpha.patch b/queue-5.10/tmpfs-disallow-config_tmpfs_inode64-on-alpha.patch new file mode 100644 index 00000000000..fd955a67886 --- /dev/null +++ b/queue-5.10/tmpfs-disallow-config_tmpfs_inode64-on-alpha.patch @@ -0,0 +1,50 @@ +From ad69c389ec110ea54f8b0c0884b255340ef1c736 Mon Sep 17 00:00:00 2001 +From: Seth Forshee +Date: Tue, 9 Feb 2021 13:42:17 -0800 +Subject: tmpfs: disallow CONFIG_TMPFS_INODE64 on alpha + +From: Seth Forshee + +commit ad69c389ec110ea54f8b0c0884b255340ef1c736 upstream. + +As with s390, alpha is a 64-bit architecture with a 32-bit ino_t. With +CONFIG_TMPFS_INODE64=y tmpfs mounts will get 64-bit inode numbers and +display "inode64" in the mount options, whereas passing "inode64" in the +mount options will fail. This leads to erroneous behaviours such as +this: + + # mkdir mnt + # mount -t tmpfs nodev mnt + # mount -o remount,rw mnt + mount: /home/ubuntu/mnt: mount point not mounted or bad option. + +Prevent CONFIG_TMPFS_INODE64 from being selected on alpha. + +Link: https://lkml.kernel.org/r/20210208215726.608197-1-seth.forshee@canonical.com +Fixes: ea3271f7196c ("tmpfs: support 64-bit inums per-sb") +Signed-off-by: Seth Forshee +Acked-by: Hugh Dickins +Cc: Chris Down +Cc: Amir Goldstein +Cc: Richard Henderson +Cc: Ivan Kokshaysky +Cc: Matt Turner +Cc: [5.9+] +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + fs/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -203,7 +203,7 @@ config TMPFS_XATTR + + config TMPFS_INODE64 + bool "Use 64-bit ino_t by default in tmpfs" +- depends on TMPFS && 64BIT && !S390 ++ depends on TMPFS && 64BIT && !(S390 || ALPHA) + default n + help + tmpfs has historically used only inode numbers as wide as an unsigned diff --git a/queue-5.10/tmpfs-disallow-config_tmpfs_inode64-on-s390.patch b/queue-5.10/tmpfs-disallow-config_tmpfs_inode64-on-s390.patch new file mode 100644 index 00000000000..6be07e812a5 --- /dev/null +++ b/queue-5.10/tmpfs-disallow-config_tmpfs_inode64-on-s390.patch @@ -0,0 +1,54 @@ +From b85a7a8bb5736998b8a681937a9749b350c17988 Mon Sep 17 00:00:00 2001 +From: Seth Forshee +Date: Tue, 9 Feb 2021 13:42:14 -0800 +Subject: tmpfs: disallow CONFIG_TMPFS_INODE64 on s390 + +From: Seth Forshee + +commit b85a7a8bb5736998b8a681937a9749b350c17988 upstream. + +Currently there is an assumption in tmpfs that 64-bit architectures also +have a 64-bit ino_t. This is not true on s390 which has a 32-bit ino_t. +With CONFIG_TMPFS_INODE64=y tmpfs mounts will get 64-bit inode numbers +and display "inode64" in the mount options, but passing the "inode64" +mount option will fail. This leads to the following behavior: + + # mkdir mnt + # mount -t tmpfs nodev mnt + # mount -o remount,rw mnt + mount: /home/ubuntu/mnt: mount point not mounted or bad option. + +As mount sees "inode64" in the mount options and thus passes it in the +options for the remount. + +So prevent CONFIG_TMPFS_INODE64 from being selected on s390. + +Link: https://lkml.kernel.org/r/20210205230620.518245-1-seth.forshee@canonical.com +Fixes: ea3271f7196c ("tmpfs: support 64-bit inums per-sb") +Signed-off-by: Seth Forshee +Acked-by: Hugh Dickins +Cc: Chris Down +Cc: Hugh Dickins +Cc: Amir Goldstein +Cc: Heiko Carstens +Cc: Vasily Gorbik +Cc: Christian Borntraeger +Cc: [5.9+] +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + fs/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/fs/Kconfig ++++ b/fs/Kconfig +@@ -203,7 +203,7 @@ config TMPFS_XATTR + + config TMPFS_INODE64 + bool "Use 64-bit ino_t by default in tmpfs" +- depends on TMPFS && 64BIT ++ depends on TMPFS && 64BIT && !S390 + default n + help + tmpfs has historically used only inode numbers as wide as an unsigned diff --git a/queue-5.10/tracing-check-length-before-giving-out-the-filter-buffer.patch b/queue-5.10/tracing-check-length-before-giving-out-the-filter-buffer.patch new file mode 100644 index 00000000000..95fb14bdd42 --- /dev/null +++ b/queue-5.10/tracing-check-length-before-giving-out-the-filter-buffer.patch @@ -0,0 +1,46 @@ +From b220c049d5196dd94d992dd2dc8cba1a5e6123bf Mon Sep 17 00:00:00 2001 +From: "Steven Rostedt (VMware)" +Date: Wed, 10 Feb 2021 11:53:22 -0500 +Subject: tracing: Check length before giving out the filter buffer + +From: Steven Rostedt (VMware) + +commit b220c049d5196dd94d992dd2dc8cba1a5e6123bf upstream. + +When filters are used by trace events, a page is allocated on each CPU and +used to copy the trace event fields to this page before writing to the ring +buffer. The reason to use the filter and not write directly into the ring +buffer is because a filter may discard the event and there's more overhead +on discarding from the ring buffer than the extra copy. + +The problem here is that there is no check against the size being allocated +when using this page. If an event asks for more than a page size while being +filtered, it will get only a page, leading to the caller writing more that +what was allocated. + +Check the length of the request, and if it is more than PAGE_SIZE minus the +header default back to allocating from the ring buffer directly. The ring +buffer may reject the event if its too big anyway, but it wont overflow. + +Link: https://lore.kernel.org/ath10k/1612839593-2308-1-git-send-email-wgong@codeaurora.org/ + +Cc: stable@vger.kernel.org +Fixes: 0fc1b09ff1ff4 ("tracing: Use temp buffer when filtering events") +Reported-by: Wen Gong +Signed-off-by: Steven Rostedt (VMware) +Signed-off-by: Greg Kroah-Hartman +--- + kernel/trace/trace.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/kernel/trace/trace.c ++++ b/kernel/trace/trace.c +@@ -2745,7 +2745,7 @@ trace_event_buffer_lock_reserve(struct t + (entry = this_cpu_read(trace_buffered_event))) { + /* Try to use the per cpu buffer first */ + val = this_cpu_inc_return(trace_buffered_event_cnt); +- if (val == 1) { ++ if ((len < (PAGE_SIZE - sizeof(*entry))) && val == 1) { + trace_event_setup(entry, type, flags, pc); + entry->array[0] = len; + return entry; diff --git a/queue-5.10/tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch b/queue-5.10/tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch new file mode 100644 index 00000000000..b367e543c72 --- /dev/null +++ b/queue-5.10/tracing-do-not-count-ftrace-events-in-top-level-enable-output.patch @@ -0,0 +1,48 @@ +From 256cfdd6fdf70c6fcf0f7c8ddb0ebd73ce8f3bc9 Mon Sep 17 00:00:00 2001 +From: "Steven Rostedt (VMware)" +Date: Fri, 5 Feb 2021 15:40:04 -0500 +Subject: tracing: Do not count ftrace events in top level enable output + +From: Steven Rostedt (VMware) + +commit 256cfdd6fdf70c6fcf0f7c8ddb0ebd73ce8f3bc9 upstream. + +The file /sys/kernel/tracing/events/enable is used to enable all events by +echoing in "1", or disabling all events when echoing in "0". To know if all +events are enabled, disabled, or some are enabled but not all of them, +cating the file should show either "1" (all enabled), "0" (all disabled), or +"X" (some enabled but not all of them). This works the same as the "enable" +files in the individule system directories (like tracing/events/sched/enable). + +But when all events are enabled, the top level "enable" file shows "X". The +reason is that its checking the "ftrace" events, which are special events +that only exist for their format files. These include the format for the +function tracer events, that are enabled when the function tracer is +enabled, but not by the "enable" file. The check includes these events, +which will always be disabled, and even though all true events are enabled, +the top level "enable" file will show "X" instead of "1". + +To fix this, have the check test the event's flags to see if it has the +"IGNORE_ENABLE" flag set, and if so, not test it. + +Cc: stable@vger.kernel.org +Fixes: 553552ce1796c ("tracing: Combine event filter_active and enable into single flags field") +Reported-by: "Yordan Karadzhov (VMware)" +Signed-off-by: Steven Rostedt (VMware) +Signed-off-by: Greg Kroah-Hartman +--- + kernel/trace/trace_events.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/kernel/trace/trace_events.c ++++ b/kernel/trace/trace_events.c +@@ -1212,7 +1212,8 @@ system_enable_read(struct file *filp, ch + mutex_lock(&event_mutex); + list_for_each_entry(file, &tr->events, list) { + call = file->event_call; +- if (!trace_event_name(call) || !call->class || !call->class->reg) ++ if ((call->flags & TRACE_EVENT_FL_IGNORE_ENABLE) || ++ !trace_event_name(call) || !call->class || !call->class->reg) + continue; + + if (system && strcmp(call->class->system, system->name) != 0)