From: segher Date: Sun, 22 Jun 2014 17:16:03 +0000 (+0000) Subject: rs6000: Merge rotlsi3 and rotldi3 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e3d83c3b12c14fe50f34b90305c56e2a9eeec672;p=thirdparty%2Fgcc.git rs6000: Merge rotlsi3 and rotldi3 This uses the rotl* extended mnemonics instead of the rlw*nm and rld*cl mnemonics, because they are shorter and more importantly they look the same for 32-bit and 64-bit. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@211878 138bc75d-0d04-0410-961f-82ee72b054a4 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 89ac3b6174cd..129713562e29 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2014-06-22 Segher Boessenkool + + * config/rs6000/rs6000.md (rotlsi3, *rotlsi3_internal2 and split, + *rotlsi3_internal3 and split, rotldi3, *rotldi3_internal2 and split, + *rotldi3_internal3 and split): Delete, merge into... + (rotl3, rotl3_dot, rotl3_dot2): New. + (*rotlsi3_64): Fix formatting. Fix condition. Replace "i" by "n". + Use "rotlw" extended mnemonic. + 2014-06-22 Segher Boessenkool * config/rs6000/rs6000.md (ashlsi3, two anonymous define_insns diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f8aca8915e94..e0332d256dfe 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3859,92 +3859,82 @@ [(set_attr "type" "shift") (set_attr "dot" "yes")]) -(define_insn "rotlsi3" - [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") - (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] + +(define_insn "rotl3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") + (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n")))] "" "@ - rlwnm %0,%1,%2,0xffffffff - rlwinm %0,%1,%h2,0xffffffff" + rotl %0,%1,%2 + rotli %0,%1,%2" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) (define_insn "*rotlsi3_64" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (zero_extend:DI + (zero_extend:DI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] - "TARGET_64BIT" + (match_operand:SI 2 "reg_or_cint_operand" "r,n"))))] + "TARGET_POWERPC64" "@ - rlwnm %0,%1,%2,0xffffffff - rlwinm %0,%1,%h2,0xffffffff" + rotlw %0,%1,%2 + rotlwi %0,%1,%h2" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no")]) -(define_insn "*rotlsi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) +(define_insn_and_split "*rotl3_dot" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "" + (clobber (match_scratch:GPR 0 "=r,r,r,r"))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - rlwnm. %3,%1,%2,0xffffffff - rlwinm. %3,%1,%h2,0xffffffff + rotl. %0,%1,%2 + rotli. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (rotate:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:SI 3 ""))] - "reload_completed" - [(set (match_dup 3) - (rotate:SI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*rotlsi3_internal3" +(define_insn_and_split "*rotl3_dot2" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) + (compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:GPR 2 "reg_or_cint_operand" "r,n,r,n")) (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") - (rotate:SI (match_dup 1) (match_dup 2)))] - "" + (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,r,r") + (rotate:GPR (match_dup 1) + (match_dup 2)))] + "mode == Pmode && rs6000_gen_cell_microcode" "@ - rlwnm. %0,%1,%2,0xffffffff - rlwinm. %0,%1,%h2,0xffffffff + rotl. %0,%1,%2 + rotli. %0,%1,%2 # #" + "&& reload_completed" + [(set (match_dup 0) + (rotate:GPR (match_dup 1) + (match_dup 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "" [(set_attr "type" "shift") (set_attr "var_shift" "yes,no,yes,no") (set_attr "dot" "yes") (set_attr "length" "4,4,8,8")]) -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "gpc_reg_operand" "") - (rotate:SI (match_dup 1) (match_dup 2)))] - "reload_completed" - [(set (match_dup 0) - (rotate:SI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") (define_insn "*rotlsi3_internal4" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") @@ -6962,81 +6952,6 @@ DONE; }) -(define_insn "rotldi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") - (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i")))] - "TARGET_POWERPC64" - "@ - rldcl %0,%1,%2,0 - rldicl %0,%1,%H2,0" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no")]) - -(define_insn "*rotldi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT" - "@ - rldcl. %3,%1,%2,0 - rldicl. %3,%1,%H2,0 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 3) - (rotate:DI (match_dup 1) (match_dup 2))) - (set (match_dup 0) - (compare:CC (match_dup 3) - (const_int 0)))] - "") - -(define_insn "*rotldi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (rotate:DI (match_dup 1) (match_dup 2)))] - "TARGET_64BIT" - "@ - rldcl. %0,%1,%2,0 - rldicl. %0,%1,%H2,0 - # - #" - [(set_attr "type" "shift") - (set_attr "var_shift" "yes,no,yes,no") - (set_attr "dot" "yes") - (set_attr "length" "4,4,8,8")]) - -(define_split - [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") - (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_cint_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (rotate:DI (match_dup 1) (match_dup 2)))] - "TARGET_POWERPC64 && reload_completed" - [(set (match_dup 0) - (rotate:DI (match_dup 1) (match_dup 2))) - (set (match_dup 3) - (compare:CC (match_dup 0) - (const_int 0)))] - "") - (define_insn "*rotldi3_internal4" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")