From: Ignacio Encinas Date: Tue, 11 Mar 2025 17:20:22 +0000 (+0100) Subject: riscv: fix test_and_{set,clear}_bit ordering documentation X-Git-Tag: v6.15-rc1~222^2~1 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e3f42c436d7e0cb432935fe3ae275dd8d9b60f71;p=thirdparty%2Fkernel%2Fstable.git riscv: fix test_and_{set,clear}_bit ordering documentation test_and_{set,clear}_bit are fully ordered as specified in Documentation/atomic_bitops.txt. Fix incorrect comment stating otherwise. Note that the implementation is correct since commit 9347ce54cd69 ("RISC-V: __test_and_op_bit_ord should be strongly ordered") was introduced. Signed-off-by: Ignacio Encinas Signed-off-by: Yury Norov --- diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index c6bd3d8354a96..49a0f48d93df5 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -226,7 +226,7 @@ legacy: * @nr: Bit to set * @addr: Address to count from * - * This operation may be reordered on other architectures than x86. + * This is an atomic fully-ordered operation (implied full memory barrier). */ static __always_inline int arch_test_and_set_bit(int nr, volatile unsigned long *addr) { @@ -238,7 +238,7 @@ static __always_inline int arch_test_and_set_bit(int nr, volatile unsigned long * @nr: Bit to clear * @addr: Address to count from * - * This operation can be reordered on other architectures other than x86. + * This is an atomic fully-ordered operation (implied full memory barrier). */ static __always_inline int arch_test_and_clear_bit(int nr, volatile unsigned long *addr) {