From: Uros Bizjak <uros@gcc.gnu.org>
Date: Thu, 28 Apr 2016 16:35:03 +0000 (+0200)
Subject: i386.md (zeroing peephole2): Use general_reg_operand.
X-Git-Tag: basepoints/gcc-8~7335
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e41ebdf1c8fa94e1bb724a939d014b5f515496f0;p=thirdparty%2Fgcc.git

i386.md (zeroing peephole2): Use general_reg_operand.

	* config/i386/i386.md (zeroing peephole2): Use general_reg_operand.
	(or $-1,reg peephole2): Ditto.
	(strict_low_part zeroing peephole2): Use SWI12 mode iterator.

From-SVN: r235581
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 52be94c01052..3defcd2adf0f 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,4 +1,10 @@
-2016-04-28  Markus Trippelsdorf  <markus@trippelsdorf.de> 
+2016-04-28  Uros Bizjak  <ubizjak@gmail.com>
+
+	* config/i386/i386.md (zeroing peephole2): Use general_reg_operand.
+	(or $-1,reg peephole2): Ditto.
+	(strict_low_part zeroing peephole2): Use SWI12 mode iterator.
+
+2016-04-28  Markus Trippelsdorf  <markus@trippelsdorf.de>
 
 	* doc/extend.texi (Common Function Attributes) [optimize]:
 	Discourage use of the optimize attribute.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 6befec76c0d0..30c0997a5232 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -18124,34 +18124,30 @@
 				copy_rtx (operands[2]));
 })
 
-;; Attempt to always use XOR for zeroing registers.
+;; Attempt to always use XOR for zeroing registers (including FP modes).
 (define_peephole2
-  [(set (match_operand 0 "register_operand")
+  [(set (match_operand 0 "general_reg_operand")
 	(match_operand 1 "const0_operand"))]
   "GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
    && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
-   && GENERAL_REGNO_P (REGNO (operands[0]))
    && peep2_regno_dead_p (0, FLAGS_REG)"
   [(parallel [(set (match_dup 0) (const_int 0))
 	      (clobber (reg:CC FLAGS_REG))])]
   "operands[0] = gen_lowpart (word_mode, operands[0]);")
 
 (define_peephole2
-  [(set (strict_low_part (match_operand 0 "register_operand"))
+  [(set (strict_low_part (match_operand:SWI12 0 "general_reg_operand"))
 	(const_int 0))]
-  "(GET_MODE (operands[0]) == QImode
-    || GET_MODE (operands[0]) == HImode)
-   && (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
+  "(! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
    && peep2_regno_dead_p (0, FLAGS_REG)"
   [(parallel [(set (strict_low_part (match_dup 0)) (const_int 0))
 	      (clobber (reg:CC FLAGS_REG))])])
 
 ;; For HI, SI and DI modes, or $-1,reg is smaller than mov $-1,reg.
 (define_peephole2
-  [(set (match_operand:SWI248 0 "register_operand")
+  [(set (match_operand:SWI248 0 "general_reg_operand")
 	(const_int -1))]
-  "(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
-   && GENERAL_REGNO_P (REGNO (operands[0]))
+  "(TARGET_MOVE_M1_VIA_OR || optimize_insn_for_size_p ())
    && peep2_regno_dead_p (0, FLAGS_REG)"
   [(parallel [(set (match_dup 0) (const_int -1))
 	      (clobber (reg:CC FLAGS_REG))])]