From: Nelson Chu <nelson@rivosinc.com>
Date: Fri, 4 Jul 2025 05:42:37 +0000 (+0800)
Subject: RISC-V: Fixed that .option push/pop won't recover the xlen
X-Git-Tag: binutils-2_45~142
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e4364b988127763e32a448123c7313b210d37045;p=thirdparty%2Fbinutils-gdb.git

RISC-V: Fixed that .option push/pop won't recover the xlen
---

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index d0030de4681..60e4f5bf813 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -332,6 +332,7 @@ struct riscv_option_stack
   struct riscv_option_stack *next;
   struct riscv_set_options options;
   riscv_subset_list_t *subset_list;
+  unsigned xlen;
 };
 
 static struct riscv_option_stack *riscv_opts_stack = NULL;
@@ -5113,6 +5114,7 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
       s->next = riscv_opts_stack;
       s->options = riscv_opts;
       s->subset_list = riscv_rps_as.subset_list;
+      s->xlen = xlen;
       riscv_opts_stack = s;
       riscv_rps_as.subset_list = riscv_copy_subset_list (s->subset_list);
     }
@@ -5129,6 +5131,7 @@ s_riscv_option (int x ATTRIBUTE_UNUSED)
 	  riscv_opts_stack = s->next;
 	  riscv_opts = s->options;
 	  riscv_rps_as.subset_list = s->subset_list;
+	  xlen = s->xlen;
 	  riscv_release_subset_list (release_subsets);
 	  free (s);
 	}
diff --git a/gas/testsuite/gas/riscv/option-norvc.d b/gas/testsuite/gas/riscv/option-norvc.d
index 13b0705fa8f..107e3f98275 100644
--- a/gas/testsuite/gas/riscv/option-norvc.d
+++ b/gas/testsuite/gas/riscv/option-norvc.d
@@ -12,11 +12,11 @@ SYMBOL TABLE:
 0+02 l       .text	0+00 \$xrv64i2p0
 0+06 l       .text	0+00 \$xrv32i2p0_f2p0_c2p0
 0+08 l       .text	0+00 \$xrv32i2p0_f2p0
-0+0c l       .text	0+00 \$xrv32i2p0_f2p0_d2p0_c2p0
-0+0e l       .text	0+00 \$xrv32i2p0_f2p0_d2p0
-0+12 l       .text	0+00 \$xrv32i2p0_f2p0_d2p0_zca1p0
+0+0c l       .text	0+00 \$xrv64i2p0_f2p0_d2p0_c2p0
+0+0e l       .text	0+00 \$xrv64i2p0_f2p0_d2p0
+0+12 l       .text	0+00 \$xrv64i2p0_f2p0_d2p0_zca1p0
 0+18 l       .text	0+00 \$xrv32i2p0_f2p0_zca1p0_zcf1p0
-0+1e l       .text	0+00 \$xrv32i2p0_f2p0_d2p0_zca1p0_zcd1p0
+0+1e l       .text	0+00 \$xrv64i2p0_f2p0_d2p0_zca1p0_zcd1p0
 0+24 l       .text	0+00 \$xrv32i2p0_zilsd1p0_zca1p0_zcb1p0_zclsd1p0
 0+30 l       .text	0+00 \$xrv64i2p0_zca1p0_zcmop1p0_zcmp1p0_zcmt1p0
 0+0 l    d  .riscv.attributes	0+00 .riscv.attributes