From: Sasha Levin Date: Tue, 15 Oct 2019 05:17:53 +0000 (-0400) Subject: fixes for 4.19 X-Git-Tag: v4.4.197~29 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e60f6d3340f09af5bbbc332fda219e31fd7d7aec;p=thirdparty%2Fkernel%2Fstable-queue.git fixes for 4.19 Signed-off-by: Sasha Levin --- diff --git a/queue-4.19/cifs-use-cifsinodeinfo-open_file_lock-while-iteratin.patch b/queue-4.19/cifs-use-cifsinodeinfo-open_file_lock-while-iteratin.patch new file mode 100644 index 00000000000..24573758938 --- /dev/null +++ b/queue-4.19/cifs-use-cifsinodeinfo-open_file_lock-while-iteratin.patch @@ -0,0 +1,169 @@ +From 67bc2a08313798ce860c8671bad3c94dcbe238b1 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 3 Oct 2019 15:16:27 +1000 +Subject: cifs: use cifsInodeInfo->open_file_lock while iterating to avoid a + panic + +From: Dave Wysochanski + +Commit 487317c99477 ("cifs: add spinlock for the openFileList to +cifsInodeInfo") added cifsInodeInfo->open_file_lock spin_lock to protect +the openFileList, but missed a few places where cifs_inode->openFileList +was enumerated. Change these remaining tcon->open_file_lock to +cifsInodeInfo->open_file_lock to avoid panic in is_size_safe_to_change. + +[17313.245641] RIP: 0010:is_size_safe_to_change+0x57/0xb0 [cifs] +[17313.245645] Code: 68 40 48 89 ef e8 19 67 b7 f1 48 8b 43 40 48 8d 4b 40 48 8d 50 f0 48 39 c1 75 0f eb 47 48 8b 42 10 48 8d 50 f0 48 39 c1 74 3a <8b> 80 88 00 00 00 83 c0 01 a8 02 74 e6 48 89 ef c6 07 00 0f 1f 40 +[17313.245649] RSP: 0018:ffff94ae1baefa30 EFLAGS: 00010202 +[17313.245654] RAX: dead000000000100 RBX: ffff88dc72243300 RCX: ffff88dc72243340 +[17313.245657] RDX: dead0000000000f0 RSI: 00000000098f7940 RDI: ffff88dd3102f040 +[17313.245659] RBP: ffff88dd3102f040 R08: 0000000000000000 R09: ffff94ae1baefc40 +[17313.245661] R10: ffffcdc8bb1c4e80 R11: ffffcdc8b50adb08 R12: 00000000098f7940 +[17313.245663] R13: ffff88dc72243300 R14: ffff88dbc8f19600 R15: ffff88dc72243428 +[17313.245667] FS: 00007fb145485700(0000) GS:ffff88dd3e000000(0000) knlGS:0000000000000000 +[17313.245670] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 +[17313.245672] CR2: 0000026bb46c6000 CR3: 0000004edb110003 CR4: 00000000007606e0 +[17313.245753] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 +[17313.245756] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 +[17313.245759] PKRU: 55555554 +[17313.245761] Call Trace: +[17313.245803] cifs_fattr_to_inode+0x16b/0x580 [cifs] +[17313.245838] cifs_get_inode_info+0x35c/0xa60 [cifs] +[17313.245852] ? kmem_cache_alloc_trace+0x151/0x1d0 +[17313.245885] cifs_open+0x38f/0x990 [cifs] +[17313.245921] ? cifs_revalidate_dentry_attr+0x3e/0x350 [cifs] +[17313.245953] ? cifsFileInfo_get+0x30/0x30 [cifs] +[17313.245960] ? do_dentry_open+0x132/0x330 +[17313.245963] do_dentry_open+0x132/0x330 +[17313.245969] path_openat+0x573/0x14d0 +[17313.245974] do_filp_open+0x93/0x100 +[17313.245979] ? __check_object_size+0xa3/0x181 +[17313.245986] ? audit_alloc_name+0x7e/0xd0 +[17313.245992] do_sys_open+0x184/0x220 +[17313.245999] do_syscall_64+0x5b/0x1b0 + +Fixes: 487317c99477 ("cifs: add spinlock for the openFileList to cifsInodeInfo") + +CC: Stable +Signed-off-by: Dave Wysochanski +Reviewed-by: Ronnie Sahlberg +Signed-off-by: Steve French +--- + fs/cifs/file.c | 27 +++++++++++---------------- + 1 file changed, 11 insertions(+), 16 deletions(-) + +diff --git a/fs/cifs/file.c b/fs/cifs/file.c +index 8703b5f26f452..26027d85ffd57 100644 +--- a/fs/cifs/file.c ++++ b/fs/cifs/file.c +@@ -1835,13 +1835,12 @@ struct cifsFileInfo *find_readable_file(struct cifsInodeInfo *cifs_inode, + { + struct cifsFileInfo *open_file = NULL; + struct cifs_sb_info *cifs_sb = CIFS_SB(cifs_inode->vfs_inode.i_sb); +- struct cifs_tcon *tcon = cifs_sb_master_tcon(cifs_sb); + + /* only filter by fsuid on multiuser mounts */ + if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_MULTIUSER)) + fsuid_only = false; + +- spin_lock(&tcon->open_file_lock); ++ spin_lock(&cifs_inode->open_file_lock); + /* we could simply get the first_list_entry since write-only entries + are always at the end of the list but since the first entry might + have a close pending, we go through the whole list */ +@@ -1853,7 +1852,7 @@ struct cifsFileInfo *find_readable_file(struct cifsInodeInfo *cifs_inode, + /* found a good file */ + /* lock it so it will not be closed on us */ + cifsFileInfo_get(open_file); +- spin_unlock(&tcon->open_file_lock); ++ spin_unlock(&cifs_inode->open_file_lock); + return open_file; + } /* else might as well continue, and look for + another, or simply have the caller reopen it +@@ -1861,7 +1860,7 @@ struct cifsFileInfo *find_readable_file(struct cifsInodeInfo *cifs_inode, + } else /* write only file */ + break; /* write only files are last so must be done */ + } +- spin_unlock(&tcon->open_file_lock); ++ spin_unlock(&cifs_inode->open_file_lock); + return NULL; + } + +@@ -1870,7 +1869,6 @@ struct cifsFileInfo *find_writable_file(struct cifsInodeInfo *cifs_inode, + { + struct cifsFileInfo *open_file, *inv_file = NULL; + struct cifs_sb_info *cifs_sb; +- struct cifs_tcon *tcon; + bool any_available = false; + int rc; + unsigned int refind = 0; +@@ -1886,16 +1884,15 @@ struct cifsFileInfo *find_writable_file(struct cifsInodeInfo *cifs_inode, + } + + cifs_sb = CIFS_SB(cifs_inode->vfs_inode.i_sb); +- tcon = cifs_sb_master_tcon(cifs_sb); + + /* only filter by fsuid on multiuser mounts */ + if (!(cifs_sb->mnt_cifs_flags & CIFS_MOUNT_MULTIUSER)) + fsuid_only = false; + +- spin_lock(&tcon->open_file_lock); ++ spin_lock(&cifs_inode->open_file_lock); + refind_writable: + if (refind > MAX_REOPEN_ATT) { +- spin_unlock(&tcon->open_file_lock); ++ spin_unlock(&cifs_inode->open_file_lock); + return NULL; + } + list_for_each_entry(open_file, &cifs_inode->openFileList, flist) { +@@ -1907,7 +1904,7 @@ struct cifsFileInfo *find_writable_file(struct cifsInodeInfo *cifs_inode, + if (!open_file->invalidHandle) { + /* found a good writable file */ + cifsFileInfo_get(open_file); +- spin_unlock(&tcon->open_file_lock); ++ spin_unlock(&cifs_inode->open_file_lock); + return open_file; + } else { + if (!inv_file) +@@ -1926,7 +1923,7 @@ struct cifsFileInfo *find_writable_file(struct cifsInodeInfo *cifs_inode, + cifsFileInfo_get(inv_file); + } + +- spin_unlock(&tcon->open_file_lock); ++ spin_unlock(&cifs_inode->open_file_lock); + + if (inv_file) { + rc = cifs_reopen_file(inv_file, false); +@@ -1940,7 +1937,7 @@ struct cifsFileInfo *find_writable_file(struct cifsInodeInfo *cifs_inode, + cifsFileInfo_put(inv_file); + ++refind; + inv_file = NULL; +- spin_lock(&tcon->open_file_lock); ++ spin_lock(&cifs_inode->open_file_lock); + goto refind_writable; + } + } +@@ -4001,17 +3998,15 @@ static int cifs_readpage(struct file *file, struct page *page) + static int is_inode_writable(struct cifsInodeInfo *cifs_inode) + { + struct cifsFileInfo *open_file; +- struct cifs_tcon *tcon = +- cifs_sb_master_tcon(CIFS_SB(cifs_inode->vfs_inode.i_sb)); + +- spin_lock(&tcon->open_file_lock); ++ spin_lock(&cifs_inode->open_file_lock); + list_for_each_entry(open_file, &cifs_inode->openFileList, flist) { + if (OPEN_FMODE(open_file->f_flags) & FMODE_WRITE) { +- spin_unlock(&tcon->open_file_lock); ++ spin_unlock(&cifs_inode->open_file_lock); + return 1; + } + } +- spin_unlock(&tcon->open_file_lock); ++ spin_unlock(&cifs_inode->open_file_lock); + return 0; + } + +-- +2.20.1 + diff --git a/queue-4.19/firmware-google-increment-vpd-key_len-properly.patch b/queue-4.19/firmware-google-increment-vpd-key_len-properly.patch new file mode 100644 index 00000000000..ade3760371f --- /dev/null +++ b/queue-4.19/firmware-google-increment-vpd-key_len-properly.patch @@ -0,0 +1,48 @@ +From c27212d9b33ec74cf4e18086616d1ee55fa0b9bb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 30 Sep 2019 14:45:22 -0700 +Subject: firmware: google: increment VPD key_len properly + +From: Brian Norris + +[ Upstream commit 442f1e746e8187b9deb1590176f6b0ff19686b11 ] + +Commit 4b708b7b1a2c ("firmware: google: check if size is valid when +decoding VPD data") adds length checks, but the new vpd_decode_entry() +function botched the logic -- it adds the key length twice, instead of +adding the key and value lengths separately. + +On my local system, this means vpd.c's vpd_section_create_attribs() hits +an error case after the first attribute it parses, since it's no longer +looking at the correct offset. With this patch, I'm back to seeing all +the correct attributes in /sys/firmware/vpd/... + +Fixes: 4b708b7b1a2c ("firmware: google: check if size is valid when decoding VPD data") +Cc: +Cc: Hung-Te Lin +Signed-off-by: Brian Norris +Reviewed-by: Stephen Boyd +Reviewed-by: Guenter Roeck +Link: https://lore.kernel.org/r/20190930214522.240680-1-briannorris@chromium.org +Signed-off-by: Greg Kroah-Hartman +Signed-off-by: Sasha Levin +--- + drivers/firmware/google/vpd_decode.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/firmware/google/vpd_decode.c b/drivers/firmware/google/vpd_decode.c +index e75abe9fa122c..6c7ab2ba85d2f 100644 +--- a/drivers/firmware/google/vpd_decode.c ++++ b/drivers/firmware/google/vpd_decode.c +@@ -62,7 +62,7 @@ static int vpd_decode_entry(const u32 max_len, const u8 *input_buf, + if (max_len - consumed < *entry_len) + return VPD_FAIL; + +- consumed += decoded_len; ++ consumed += *entry_len; + *_consumed = consumed; + return VPD_OK; + } +-- +2.20.1 + diff --git a/queue-4.19/gpiolib-don-t-clear-flag_is_out-when-emulating-open-.patch b/queue-4.19/gpiolib-don-t-clear-flag_is_out-when-emulating-open-.patch new file mode 100644 index 00000000000..57749a02f77 --- /dev/null +++ b/queue-4.19/gpiolib-don-t-clear-flag_is_out-when-emulating-open-.patch @@ -0,0 +1,99 @@ +From 55eaa2df9d0fd576520eef0f70c56350d37ce6a7 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 14 Oct 2019 17:54:35 +0200 +Subject: gpiolib: don't clear FLAG_IS_OUT when emulating + open-drain/open-source + +From: Bartosz Golaszewski + +[ Upstream commit e735244e2cf068f98b6384681a38993e0517a838 ] + +When emulating open-drain/open-source by not actively driving the output +lines - we're simply changing their mode to input. This is wrong as it +will then make it impossible to change the value of such line - it's now +considered to actually be in input mode. If we want to still use the +direction_input() callback for simplicity then we need to set FLAG_IS_OUT +manually in gpiod_direction_output() and not clear it in +gpio_set_open_drain_value_commit() and +gpio_set_open_source_value_commit(). + +Fixes: c663e5f56737 ("gpio: support native single-ended hardware drivers") +Cc: stable@vger.kernel.org +Reported-by: Kent Gibson +Signed-off-by: Bartosz Golaszewski +[Bartosz: backported to v5.3, v4.19] +Signed-off-by: Bartosz Golaszewski +Signed-off-by: Sasha Levin +--- + drivers/gpio/gpiolib.c | 27 +++++++++++++++++++-------- + 1 file changed, 19 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +index 3289b53a7ba14..565ab945698ca 100644 +--- a/drivers/gpio/gpiolib.c ++++ b/drivers/gpio/gpiolib.c +@@ -2649,8 +2649,10 @@ int gpiod_direction_output(struct gpio_desc *desc, int value) + if (!ret) + goto set_output_value; + /* Emulate open drain by not actively driving the line high */ +- if (value) +- return gpiod_direction_input(desc); ++ if (value) { ++ ret = gpiod_direction_input(desc); ++ goto set_output_flag; ++ } + } + else if (test_bit(FLAG_OPEN_SOURCE, &desc->flags)) { + ret = gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc), +@@ -2658,8 +2660,10 @@ int gpiod_direction_output(struct gpio_desc *desc, int value) + if (!ret) + goto set_output_value; + /* Emulate open source by not actively driving the line low */ +- if (!value) +- return gpiod_direction_input(desc); ++ if (!value) { ++ ret = gpiod_direction_input(desc); ++ goto set_output_flag; ++ } + } else { + gpio_set_drive_single_ended(gc, gpio_chip_hwgpio(desc), + PIN_CONFIG_DRIVE_PUSH_PULL); +@@ -2667,6 +2671,17 @@ int gpiod_direction_output(struct gpio_desc *desc, int value) + + set_output_value: + return gpiod_direction_output_raw_commit(desc, value); ++ ++set_output_flag: ++ /* ++ * When emulating open-source or open-drain functionalities by not ++ * actively driving the line (setting mode to input) we still need to ++ * set the IS_OUT flag or otherwise we won't be able to set the line ++ * value anymore. ++ */ ++ if (ret == 0) ++ set_bit(FLAG_IS_OUT, &desc->flags); ++ return ret; + } + EXPORT_SYMBOL_GPL(gpiod_direction_output); + +@@ -2980,8 +2995,6 @@ static void gpio_set_open_drain_value_commit(struct gpio_desc *desc, bool value) + + if (value) { + err = chip->direction_input(chip, offset); +- if (!err) +- clear_bit(FLAG_IS_OUT, &desc->flags); + } else { + err = chip->direction_output(chip, offset, 0); + if (!err) +@@ -3011,8 +3024,6 @@ static void gpio_set_open_source_value_commit(struct gpio_desc *desc, bool value + set_bit(FLAG_IS_OUT, &desc->flags); + } else { + err = chip->direction_input(chip, offset); +- if (!err) +- clear_bit(FLAG_IS_OUT, &desc->flags); + } + trace_gpio_direction(desc_to_gpio(desc), !value, err); + if (err < 0) +-- +2.20.1 + diff --git a/queue-4.19/iio-adc-stm32-adc-fix-a-race-when-using-several-adcs.patch b/queue-4.19/iio-adc-stm32-adc-fix-a-race-when-using-several-adcs.patch new file mode 100644 index 00000000000..f05145ae302 --- /dev/null +++ b/queue-4.19/iio-adc-stm32-adc-fix-a-race-when-using-several-adcs.patch @@ -0,0 +1,136 @@ +From 794fdf2e903d9984fb5814710984882a68afc4dc Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 17 Sep 2019 14:38:16 +0200 +Subject: iio: adc: stm32-adc: fix a race when using several adcs with dma and + irq + +From: Fabrice Gasnier + +[ Upstream commit dcb10920179ab74caf88a6f2afadecfc2743b910 ] + +End of conversion may be handled by using IRQ or DMA. There may be a +race when two conversions complete at the same time on several ADCs. +EOC can be read as 'set' for several ADCs, with: +- an ADC configured to use IRQs. EOCIE bit is set. The handler is normally + called in this case. +- an ADC configured to use DMA. EOCIE bit isn't set. EOC triggers the DMA + request instead. It's then automatically cleared by DMA read. But the + handler gets called due to status bit is temporarily set (IRQ triggered + by the other ADC). +So both EOC status bit in CSR and EOCIE control bit must be checked +before invoking the interrupt handler (e.g. call ISR only for +IRQ-enabled ADCs). + +Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support") + +Signed-off-by: Fabrice Gasnier +Cc: +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/adc/stm32-adc-core.c | 43 +++++++++++++++++++++++++++++--- + drivers/iio/adc/stm32-adc-core.h | 1 + + 2 files changed, 41 insertions(+), 3 deletions(-) + +diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c +index ce2cc61395d63..38eb966930793 100644 +--- a/drivers/iio/adc/stm32-adc-core.c ++++ b/drivers/iio/adc/stm32-adc-core.c +@@ -27,12 +27,16 @@ + * @eoc1: adc1 end of conversion flag in @csr + * @eoc2: adc2 end of conversion flag in @csr + * @eoc3: adc3 end of conversion flag in @csr ++ * @ier: interrupt enable register offset for each adc ++ * @eocie_msk: end of conversion interrupt enable mask in @ier + */ + struct stm32_adc_common_regs { + u32 csr; + u32 eoc1_msk; + u32 eoc2_msk; + u32 eoc3_msk; ++ u32 ier; ++ u32 eocie_msk; + }; + + struct stm32_adc_priv; +@@ -241,6 +245,8 @@ static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { + .eoc1_msk = STM32F4_EOC1, + .eoc2_msk = STM32F4_EOC2, + .eoc3_msk = STM32F4_EOC3, ++ .ier = STM32F4_ADC_CR1, ++ .eocie_msk = STM32F4_EOCIE, + }; + + /* STM32H7 common registers definitions */ +@@ -248,8 +254,24 @@ static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { + .csr = STM32H7_ADC_CSR, + .eoc1_msk = STM32H7_EOC_MST, + .eoc2_msk = STM32H7_EOC_SLV, ++ .ier = STM32H7_ADC_IER, ++ .eocie_msk = STM32H7_EOCIE, + }; + ++static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = { ++ 0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2, ++}; ++ ++static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv, ++ unsigned int adc) ++{ ++ u32 ier, offset = stm32_adc_offset[adc]; ++ ++ ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier); ++ ++ return ier & priv->cfg->regs->eocie_msk; ++} ++ + /* ADC common interrupt for all instances */ + static void stm32_adc_irq_handler(struct irq_desc *desc) + { +@@ -260,13 +282,28 @@ static void stm32_adc_irq_handler(struct irq_desc *desc) + chained_irq_enter(chip, desc); + status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); + +- if (status & priv->cfg->regs->eoc1_msk) ++ /* ++ * End of conversion may be handled by using IRQ or DMA. There may be a ++ * race here when two conversions complete at the same time on several ++ * ADCs. EOC may be read 'set' for several ADCs, with: ++ * - an ADC configured to use DMA (EOC triggers the DMA request, and ++ * is then automatically cleared by DR read in hardware) ++ * - an ADC configured to use IRQs (EOCIE bit is set. The handler must ++ * be called in this case) ++ * So both EOC status bit in CSR and EOCIE control bit must be checked ++ * before invoking the interrupt handler (e.g. call ISR only for ++ * IRQ-enabled ADCs). ++ */ ++ if (status & priv->cfg->regs->eoc1_msk && ++ stm32_adc_eoc_enabled(priv, 0)) + generic_handle_irq(irq_find_mapping(priv->domain, 0)); + +- if (status & priv->cfg->regs->eoc2_msk) ++ if (status & priv->cfg->regs->eoc2_msk && ++ stm32_adc_eoc_enabled(priv, 1)) + generic_handle_irq(irq_find_mapping(priv->domain, 1)); + +- if (status & priv->cfg->regs->eoc3_msk) ++ if (status & priv->cfg->regs->eoc3_msk && ++ stm32_adc_eoc_enabled(priv, 2)) + generic_handle_irq(irq_find_mapping(priv->domain, 2)); + + chained_irq_exit(chip, desc); +diff --git a/drivers/iio/adc/stm32-adc-core.h b/drivers/iio/adc/stm32-adc-core.h +index 94aa2d2577dc9..2579d514c2a34 100644 +--- a/drivers/iio/adc/stm32-adc-core.h ++++ b/drivers/iio/adc/stm32-adc-core.h +@@ -25,6 +25,7 @@ + * -------------------------------------------------------- + */ + #define STM32_ADC_MAX_ADCS 3 ++#define STM32_ADC_OFFSET 0x100 + #define STM32_ADCX_COMN_OFFSET 0x300 + + /* STM32F4 - Registers for each ADC instance */ +-- +2.20.1 + diff --git a/queue-4.19/iio-adc-stm32-adc-move-registers-definitions.patch b/queue-4.19/iio-adc-stm32-adc-move-registers-definitions.patch new file mode 100644 index 00000000000..f56087701a5 --- /dev/null +++ b/queue-4.19/iio-adc-stm32-adc-move-registers-definitions.patch @@ -0,0 +1,336 @@ +From 677b69eb73aa265e2f4e534a5568ab0e122e57cb Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 17 Sep 2019 14:38:15 +0200 +Subject: iio: adc: stm32-adc: move registers definitions + +From: Fabrice Gasnier + +[ Upstream commit 31922f62bb527d749b99dbc776e514bcba29b7fe ] + +Move STM32 ADC registers definitions to common header. +This is precursor patch to: +- iio: adc: stm32-adc: fix a race when using several adcs with dma and irq + +It keeps registers definitions as a whole block, to ease readability and +allow simple access path to EOC bits (readl) in stm32-adc-core driver. + +Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support") + +Signed-off-by: Fabrice Gasnier +Cc: +Signed-off-by: Jonathan Cameron +Signed-off-by: Sasha Levin +--- + drivers/iio/adc/stm32-adc-core.c | 27 ------ + drivers/iio/adc/stm32-adc-core.h | 136 +++++++++++++++++++++++++++++++ + drivers/iio/adc/stm32-adc.c | 109 ------------------------- + 3 files changed, 136 insertions(+), 136 deletions(-) + +diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c +index ca432e7b6ff1d..ce2cc61395d63 100644 +--- a/drivers/iio/adc/stm32-adc-core.c ++++ b/drivers/iio/adc/stm32-adc-core.c +@@ -21,33 +21,6 @@ + + #include "stm32-adc-core.h" + +-/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ +-#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) +-#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) +- +-/* STM32F4_ADC_CSR - bit fields */ +-#define STM32F4_EOC3 BIT(17) +-#define STM32F4_EOC2 BIT(9) +-#define STM32F4_EOC1 BIT(1) +- +-/* STM32F4_ADC_CCR - bit fields */ +-#define STM32F4_ADC_ADCPRE_SHIFT 16 +-#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16) +- +-/* STM32H7 - common registers for all ADC instances */ +-#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) +-#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) +- +-/* STM32H7_ADC_CSR - bit fields */ +-#define STM32H7_EOC_SLV BIT(18) +-#define STM32H7_EOC_MST BIT(2) +- +-/* STM32H7_ADC_CCR - bit fields */ +-#define STM32H7_PRESC_SHIFT 18 +-#define STM32H7_PRESC_MASK GENMASK(21, 18) +-#define STM32H7_CKMODE_SHIFT 16 +-#define STM32H7_CKMODE_MASK GENMASK(17, 16) +- + /** + * stm32_adc_common_regs - stm32 common registers, compatible dependent data + * @csr: common status register offset +diff --git a/drivers/iio/adc/stm32-adc-core.h b/drivers/iio/adc/stm32-adc-core.h +index 8af507b3f32d9..94aa2d2577dc9 100644 +--- a/drivers/iio/adc/stm32-adc-core.h ++++ b/drivers/iio/adc/stm32-adc-core.h +@@ -27,6 +27,142 @@ + #define STM32_ADC_MAX_ADCS 3 + #define STM32_ADCX_COMN_OFFSET 0x300 + ++/* STM32F4 - Registers for each ADC instance */ ++#define STM32F4_ADC_SR 0x00 ++#define STM32F4_ADC_CR1 0x04 ++#define STM32F4_ADC_CR2 0x08 ++#define STM32F4_ADC_SMPR1 0x0C ++#define STM32F4_ADC_SMPR2 0x10 ++#define STM32F4_ADC_HTR 0x24 ++#define STM32F4_ADC_LTR 0x28 ++#define STM32F4_ADC_SQR1 0x2C ++#define STM32F4_ADC_SQR2 0x30 ++#define STM32F4_ADC_SQR3 0x34 ++#define STM32F4_ADC_JSQR 0x38 ++#define STM32F4_ADC_JDR1 0x3C ++#define STM32F4_ADC_JDR2 0x40 ++#define STM32F4_ADC_JDR3 0x44 ++#define STM32F4_ADC_JDR4 0x48 ++#define STM32F4_ADC_DR 0x4C ++ ++/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */ ++#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) ++#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04) ++ ++/* STM32F4_ADC_SR - bit fields */ ++#define STM32F4_STRT BIT(4) ++#define STM32F4_EOC BIT(1) ++ ++/* STM32F4_ADC_CR1 - bit fields */ ++#define STM32F4_RES_SHIFT 24 ++#define STM32F4_RES_MASK GENMASK(25, 24) ++#define STM32F4_SCAN BIT(8) ++#define STM32F4_EOCIE BIT(5) ++ ++/* STM32F4_ADC_CR2 - bit fields */ ++#define STM32F4_SWSTART BIT(30) ++#define STM32F4_EXTEN_SHIFT 28 ++#define STM32F4_EXTEN_MASK GENMASK(29, 28) ++#define STM32F4_EXTSEL_SHIFT 24 ++#define STM32F4_EXTSEL_MASK GENMASK(27, 24) ++#define STM32F4_EOCS BIT(10) ++#define STM32F4_DDS BIT(9) ++#define STM32F4_DMA BIT(8) ++#define STM32F4_ADON BIT(0) ++ ++/* STM32F4_ADC_CSR - bit fields */ ++#define STM32F4_EOC3 BIT(17) ++#define STM32F4_EOC2 BIT(9) ++#define STM32F4_EOC1 BIT(1) ++ ++/* STM32F4_ADC_CCR - bit fields */ ++#define STM32F4_ADC_ADCPRE_SHIFT 16 ++#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16) ++ ++/* STM32H7 - Registers for each ADC instance */ ++#define STM32H7_ADC_ISR 0x00 ++#define STM32H7_ADC_IER 0x04 ++#define STM32H7_ADC_CR 0x08 ++#define STM32H7_ADC_CFGR 0x0C ++#define STM32H7_ADC_SMPR1 0x14 ++#define STM32H7_ADC_SMPR2 0x18 ++#define STM32H7_ADC_PCSEL 0x1C ++#define STM32H7_ADC_SQR1 0x30 ++#define STM32H7_ADC_SQR2 0x34 ++#define STM32H7_ADC_SQR3 0x38 ++#define STM32H7_ADC_SQR4 0x3C ++#define STM32H7_ADC_DR 0x40 ++#define STM32H7_ADC_DIFSEL 0xC0 ++#define STM32H7_ADC_CALFACT 0xC4 ++#define STM32H7_ADC_CALFACT2 0xC8 ++ ++/* STM32H7 - common registers for all ADC instances */ ++#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00) ++#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08) ++ ++/* STM32H7_ADC_ISR - bit fields */ ++#define STM32MP1_VREGREADY BIT(12) ++#define STM32H7_EOC BIT(2) ++#define STM32H7_ADRDY BIT(0) ++ ++/* STM32H7_ADC_IER - bit fields */ ++#define STM32H7_EOCIE STM32H7_EOC ++ ++/* STM32H7_ADC_CR - bit fields */ ++#define STM32H7_ADCAL BIT(31) ++#define STM32H7_ADCALDIF BIT(30) ++#define STM32H7_DEEPPWD BIT(29) ++#define STM32H7_ADVREGEN BIT(28) ++#define STM32H7_LINCALRDYW6 BIT(27) ++#define STM32H7_LINCALRDYW5 BIT(26) ++#define STM32H7_LINCALRDYW4 BIT(25) ++#define STM32H7_LINCALRDYW3 BIT(24) ++#define STM32H7_LINCALRDYW2 BIT(23) ++#define STM32H7_LINCALRDYW1 BIT(22) ++#define STM32H7_ADCALLIN BIT(16) ++#define STM32H7_BOOST BIT(8) ++#define STM32H7_ADSTP BIT(4) ++#define STM32H7_ADSTART BIT(2) ++#define STM32H7_ADDIS BIT(1) ++#define STM32H7_ADEN BIT(0) ++ ++/* STM32H7_ADC_CFGR bit fields */ ++#define STM32H7_EXTEN_SHIFT 10 ++#define STM32H7_EXTEN_MASK GENMASK(11, 10) ++#define STM32H7_EXTSEL_SHIFT 5 ++#define STM32H7_EXTSEL_MASK GENMASK(9, 5) ++#define STM32H7_RES_SHIFT 2 ++#define STM32H7_RES_MASK GENMASK(4, 2) ++#define STM32H7_DMNGT_SHIFT 0 ++#define STM32H7_DMNGT_MASK GENMASK(1, 0) ++ ++enum stm32h7_adc_dmngt { ++ STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ ++ STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ ++ STM32H7_DMNGT_DFSDM, /* DFSDM mode */ ++ STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ ++}; ++ ++/* STM32H7_ADC_CALFACT - bit fields */ ++#define STM32H7_CALFACT_D_SHIFT 16 ++#define STM32H7_CALFACT_D_MASK GENMASK(26, 16) ++#define STM32H7_CALFACT_S_SHIFT 0 ++#define STM32H7_CALFACT_S_MASK GENMASK(10, 0) ++ ++/* STM32H7_ADC_CALFACT2 - bit fields */ ++#define STM32H7_LINCALFACT_SHIFT 0 ++#define STM32H7_LINCALFACT_MASK GENMASK(29, 0) ++ ++/* STM32H7_ADC_CSR - bit fields */ ++#define STM32H7_EOC_SLV BIT(18) ++#define STM32H7_EOC_MST BIT(2) ++ ++/* STM32H7_ADC_CCR - bit fields */ ++#define STM32H7_PRESC_SHIFT 18 ++#define STM32H7_PRESC_MASK GENMASK(21, 18) ++#define STM32H7_CKMODE_SHIFT 16 ++#define STM32H7_CKMODE_MASK GENMASK(17, 16) ++ + /** + * struct stm32_adc_common - stm32 ADC driver common data (for all instances) + * @base: control registers base cpu addr +diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c +index 378411853d751..c52d20f7ca2ed 100644 +--- a/drivers/iio/adc/stm32-adc.c ++++ b/drivers/iio/adc/stm32-adc.c +@@ -27,115 +27,6 @@ + + #include "stm32-adc-core.h" + +-/* STM32F4 - Registers for each ADC instance */ +-#define STM32F4_ADC_SR 0x00 +-#define STM32F4_ADC_CR1 0x04 +-#define STM32F4_ADC_CR2 0x08 +-#define STM32F4_ADC_SMPR1 0x0C +-#define STM32F4_ADC_SMPR2 0x10 +-#define STM32F4_ADC_HTR 0x24 +-#define STM32F4_ADC_LTR 0x28 +-#define STM32F4_ADC_SQR1 0x2C +-#define STM32F4_ADC_SQR2 0x30 +-#define STM32F4_ADC_SQR3 0x34 +-#define STM32F4_ADC_JSQR 0x38 +-#define STM32F4_ADC_JDR1 0x3C +-#define STM32F4_ADC_JDR2 0x40 +-#define STM32F4_ADC_JDR3 0x44 +-#define STM32F4_ADC_JDR4 0x48 +-#define STM32F4_ADC_DR 0x4C +- +-/* STM32F4_ADC_SR - bit fields */ +-#define STM32F4_STRT BIT(4) +-#define STM32F4_EOC BIT(1) +- +-/* STM32F4_ADC_CR1 - bit fields */ +-#define STM32F4_RES_SHIFT 24 +-#define STM32F4_RES_MASK GENMASK(25, 24) +-#define STM32F4_SCAN BIT(8) +-#define STM32F4_EOCIE BIT(5) +- +-/* STM32F4_ADC_CR2 - bit fields */ +-#define STM32F4_SWSTART BIT(30) +-#define STM32F4_EXTEN_SHIFT 28 +-#define STM32F4_EXTEN_MASK GENMASK(29, 28) +-#define STM32F4_EXTSEL_SHIFT 24 +-#define STM32F4_EXTSEL_MASK GENMASK(27, 24) +-#define STM32F4_EOCS BIT(10) +-#define STM32F4_DDS BIT(9) +-#define STM32F4_DMA BIT(8) +-#define STM32F4_ADON BIT(0) +- +-/* STM32H7 - Registers for each ADC instance */ +-#define STM32H7_ADC_ISR 0x00 +-#define STM32H7_ADC_IER 0x04 +-#define STM32H7_ADC_CR 0x08 +-#define STM32H7_ADC_CFGR 0x0C +-#define STM32H7_ADC_SMPR1 0x14 +-#define STM32H7_ADC_SMPR2 0x18 +-#define STM32H7_ADC_PCSEL 0x1C +-#define STM32H7_ADC_SQR1 0x30 +-#define STM32H7_ADC_SQR2 0x34 +-#define STM32H7_ADC_SQR3 0x38 +-#define STM32H7_ADC_SQR4 0x3C +-#define STM32H7_ADC_DR 0x40 +-#define STM32H7_ADC_DIFSEL 0xC0 +-#define STM32H7_ADC_CALFACT 0xC4 +-#define STM32H7_ADC_CALFACT2 0xC8 +- +-/* STM32H7_ADC_ISR - bit fields */ +-#define STM32MP1_VREGREADY BIT(12) +-#define STM32H7_EOC BIT(2) +-#define STM32H7_ADRDY BIT(0) +- +-/* STM32H7_ADC_IER - bit fields */ +-#define STM32H7_EOCIE STM32H7_EOC +- +-/* STM32H7_ADC_CR - bit fields */ +-#define STM32H7_ADCAL BIT(31) +-#define STM32H7_ADCALDIF BIT(30) +-#define STM32H7_DEEPPWD BIT(29) +-#define STM32H7_ADVREGEN BIT(28) +-#define STM32H7_LINCALRDYW6 BIT(27) +-#define STM32H7_LINCALRDYW5 BIT(26) +-#define STM32H7_LINCALRDYW4 BIT(25) +-#define STM32H7_LINCALRDYW3 BIT(24) +-#define STM32H7_LINCALRDYW2 BIT(23) +-#define STM32H7_LINCALRDYW1 BIT(22) +-#define STM32H7_ADCALLIN BIT(16) +-#define STM32H7_BOOST BIT(8) +-#define STM32H7_ADSTP BIT(4) +-#define STM32H7_ADSTART BIT(2) +-#define STM32H7_ADDIS BIT(1) +-#define STM32H7_ADEN BIT(0) +- +-/* STM32H7_ADC_CFGR bit fields */ +-#define STM32H7_EXTEN_SHIFT 10 +-#define STM32H7_EXTEN_MASK GENMASK(11, 10) +-#define STM32H7_EXTSEL_SHIFT 5 +-#define STM32H7_EXTSEL_MASK GENMASK(9, 5) +-#define STM32H7_RES_SHIFT 2 +-#define STM32H7_RES_MASK GENMASK(4, 2) +-#define STM32H7_DMNGT_SHIFT 0 +-#define STM32H7_DMNGT_MASK GENMASK(1, 0) +- +-enum stm32h7_adc_dmngt { +- STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */ +- STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */ +- STM32H7_DMNGT_DFSDM, /* DFSDM mode */ +- STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */ +-}; +- +-/* STM32H7_ADC_CALFACT - bit fields */ +-#define STM32H7_CALFACT_D_SHIFT 16 +-#define STM32H7_CALFACT_D_MASK GENMASK(26, 16) +-#define STM32H7_CALFACT_S_SHIFT 0 +-#define STM32H7_CALFACT_S_MASK GENMASK(10, 0) +- +-/* STM32H7_ADC_CALFACT2 - bit fields */ +-#define STM32H7_LINCALFACT_SHIFT 0 +-#define STM32H7_LINCALFACT_MASK GENMASK(29, 0) +- + /* Number of linear calibration shadow registers / LINCALRDYW control bits */ + #define STM32H7_LINCALFACT_NUM 6 + +-- +2.20.1 + diff --git a/queue-4.19/series b/queue-4.19/series index d91f4d3d426..2ce7c4309d3 100644 --- a/queue-4.19/series +++ b/queue-4.19/series @@ -55,3 +55,8 @@ cifs-force-revalidate-inode-when-dentry-is-stale.patch cifs-force-reval-dentry-if-lookup_reval-flag-is-set.patch kernel-sysctl.c-do-not-override-max_threads-provided-by-userspace.patch mm-vmpressure.c-fix-a-signedness-bug-in-vmpressure_register_event.patch +firmware-google-increment-vpd-key_len-properly.patch +gpiolib-don-t-clear-flag_is_out-when-emulating-open-.patch +iio-adc-stm32-adc-move-registers-definitions.patch +iio-adc-stm32-adc-fix-a-race-when-using-several-adcs.patch +cifs-use-cifsinodeinfo-open_file_lock-while-iteratin.patch