From: Greg Kroah-Hartman Date: Sun, 28 May 2023 14:44:22 +0000 (+0100) Subject: 6.3-stable patches X-Git-Tag: review~37 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e6d125bede149ef5ca1594b6338855bcaba09123;p=thirdparty%2Fkernel%2Fstable-queue.git 6.3-stable patches added patches: irqchip-mips-gic-don-t-touch-vl_map-if-a-local-interrupt-is-not-routable.patch irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch perf-x86-uncore-correct-the-number-of-chas-on-spr.patch x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch --- diff --git a/queue-6.3/irqchip-mips-gic-don-t-touch-vl_map-if-a-local-interrupt-is-not-routable.patch b/queue-6.3/irqchip-mips-gic-don-t-touch-vl_map-if-a-local-interrupt-is-not-routable.patch new file mode 100644 index 00000000000..32fa75c5255 --- /dev/null +++ b/queue-6.3/irqchip-mips-gic-don-t-touch-vl_map-if-a-local-interrupt-is-not-routable.patch @@ -0,0 +1,45 @@ +From 2c6c9c049510163090b979ea5f92a68ae8d93c45 Mon Sep 17 00:00:00 2001 +From: Jiaxun Yang +Date: Mon, 24 Apr 2023 11:31:55 +0100 +Subject: irqchip/mips-gic: Don't touch vl_map if a local interrupt is not routable + +From: Jiaxun Yang + +commit 2c6c9c049510163090b979ea5f92a68ae8d93c45 upstream. + +When a GIC local interrupt is not routable, it's vl_map will be used +to control some internal states for core (providing IPTI, IPPCI, IPFDC +input signal for core). Overriding it will interfere core's intetrupt +controller. + +Do not touch vl_map if a local interrupt is not routable, we are not +going to remap it. + +Before dd098a0e0319 (" irqchip/mips-gic: Get rid of the reliance on +irq_cpu_online()"), if a local interrupt is not routable, then it won't +be requested from GIC Local domain, and thus gic_all_vpes_irq_cpu_online +won't be called for that particular interrupt. + +Fixes: dd098a0e0319 (" irqchip/mips-gic: Get rid of the reliance on irq_cpu_online()") +Cc: stable@vger.kernel.org +Signed-off-by: Jiaxun Yang +Reviewed-by: Serge Semin +Tested-by: Serge Semin +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20230424103156.66753-2-jiaxun.yang@flygoat.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/irqchip/irq-mips-gic.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/irqchip/irq-mips-gic.c ++++ b/drivers/irqchip/irq-mips-gic.c +@@ -400,6 +400,8 @@ static void gic_all_vpes_irq_cpu_online( + unsigned int intr = local_intrs[i]; + struct gic_all_vpes_chip_data *cd; + ++ if (!gic_local_irq_is_routable(intr)) ++ continue; + cd = &gic_all_vpes_chip_data[intr]; + write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map); + if (cd->mask) diff --git a/queue-6.3/irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch b/queue-6.3/irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch new file mode 100644 index 00000000000..df66e7054cd --- /dev/null +++ b/queue-6.3/irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch @@ -0,0 +1,158 @@ +From 3d6a0e4197c04599d75d85a608c8bb16a630a38c Mon Sep 17 00:00:00 2001 +From: Jiaxun Yang +Date: Mon, 24 Apr 2023 11:31:56 +0100 +Subject: irqchip/mips-gic: Use raw spinlock for gic_lock + +From: Jiaxun Yang + +commit 3d6a0e4197c04599d75d85a608c8bb16a630a38c upstream. + +Since we may hold gic_lock in hardirq context, use raw spinlock +makes more sense given that it is for low-level interrupt handling +routine and the critical section is small. + +Fixes BUG: + +[ 0.426106] ============================= +[ 0.426257] [ BUG: Invalid wait context ] +[ 0.426422] 6.3.0-rc7-next-20230421-dirty #54 Not tainted +[ 0.426638] ----------------------------- +[ 0.426766] swapper/0/1 is trying to lock: +[ 0.426954] ffffffff8104e7b8 (gic_lock){....}-{3:3}, at: gic_set_type+0x30/08 + +Fixes: 95150ae8b330 ("irqchip: mips-gic: Implement irq_set_type callback") +Cc: stable@vger.kernel.org +Signed-off-by: Jiaxun Yang +Reviewed-by: Serge Semin +Tested-by: Serge Semin +Signed-off-by: Marc Zyngier +Link: https://lore.kernel.org/r/20230424103156.66753-3-jiaxun.yang@flygoat.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/irqchip/irq-mips-gic.c | 30 +++++++++++++++--------------- + 1 file changed, 15 insertions(+), 15 deletions(-) + +--- a/drivers/irqchip/irq-mips-gic.c ++++ b/drivers/irqchip/irq-mips-gic.c +@@ -50,7 +50,7 @@ void __iomem *mips_gic_base; + + static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks); + +-static DEFINE_SPINLOCK(gic_lock); ++static DEFINE_RAW_SPINLOCK(gic_lock); + static struct irq_domain *gic_irq_domain; + static int gic_shared_intrs; + static unsigned int gic_cpu_pin; +@@ -211,7 +211,7 @@ static int gic_set_type(struct irq_data + + irq = GIC_HWIRQ_TO_SHARED(d->hwirq); + +- spin_lock_irqsave(&gic_lock, flags); ++ raw_spin_lock_irqsave(&gic_lock, flags); + switch (type & IRQ_TYPE_SENSE_MASK) { + case IRQ_TYPE_EDGE_FALLING: + pol = GIC_POL_FALLING_EDGE; +@@ -251,7 +251,7 @@ static int gic_set_type(struct irq_data + else + irq_set_chip_handler_name_locked(d, &gic_level_irq_controller, + handle_level_irq, NULL); +- spin_unlock_irqrestore(&gic_lock, flags); ++ raw_spin_unlock_irqrestore(&gic_lock, flags); + + return 0; + } +@@ -269,7 +269,7 @@ static int gic_set_affinity(struct irq_d + return -EINVAL; + + /* Assumption : cpumask refers to a single CPU */ +- spin_lock_irqsave(&gic_lock, flags); ++ raw_spin_lock_irqsave(&gic_lock, flags); + + /* Re-route this IRQ */ + write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu))); +@@ -280,7 +280,7 @@ static int gic_set_affinity(struct irq_d + set_bit(irq, per_cpu_ptr(pcpu_masks, cpu)); + + irq_data_update_effective_affinity(d, cpumask_of(cpu)); +- spin_unlock_irqrestore(&gic_lock, flags); ++ raw_spin_unlock_irqrestore(&gic_lock, flags); + + return IRQ_SET_MASK_OK; + } +@@ -358,12 +358,12 @@ static void gic_mask_local_irq_all_vpes( + cd = irq_data_get_irq_chip_data(d); + cd->mask = false; + +- spin_lock_irqsave(&gic_lock, flags); ++ raw_spin_lock_irqsave(&gic_lock, flags); + for_each_online_cpu(cpu) { + write_gic_vl_other(mips_cm_vp_id(cpu)); + write_gic_vo_rmask(BIT(intr)); + } +- spin_unlock_irqrestore(&gic_lock, flags); ++ raw_spin_unlock_irqrestore(&gic_lock, flags); + } + + static void gic_unmask_local_irq_all_vpes(struct irq_data *d) +@@ -376,12 +376,12 @@ static void gic_unmask_local_irq_all_vpe + cd = irq_data_get_irq_chip_data(d); + cd->mask = true; + +- spin_lock_irqsave(&gic_lock, flags); ++ raw_spin_lock_irqsave(&gic_lock, flags); + for_each_online_cpu(cpu) { + write_gic_vl_other(mips_cm_vp_id(cpu)); + write_gic_vo_smask(BIT(intr)); + } +- spin_unlock_irqrestore(&gic_lock, flags); ++ raw_spin_unlock_irqrestore(&gic_lock, flags); + } + + static void gic_all_vpes_irq_cpu_online(void) +@@ -394,7 +394,7 @@ static void gic_all_vpes_irq_cpu_online( + unsigned long flags; + int i; + +- spin_lock_irqsave(&gic_lock, flags); ++ raw_spin_lock_irqsave(&gic_lock, flags); + + for (i = 0; i < ARRAY_SIZE(local_intrs); i++) { + unsigned int intr = local_intrs[i]; +@@ -408,7 +408,7 @@ static void gic_all_vpes_irq_cpu_online( + write_gic_vl_smask(BIT(intr)); + } + +- spin_unlock_irqrestore(&gic_lock, flags); ++ raw_spin_unlock_irqrestore(&gic_lock, flags); + } + + static struct irq_chip gic_all_vpes_local_irq_controller = { +@@ -438,11 +438,11 @@ static int gic_shared_irq_domain_map(str + + data = irq_get_irq_data(virq); + +- spin_lock_irqsave(&gic_lock, flags); ++ raw_spin_lock_irqsave(&gic_lock, flags); + write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin); + write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu))); + irq_data_update_effective_affinity(data, cpumask_of(cpu)); +- spin_unlock_irqrestore(&gic_lock, flags); ++ raw_spin_unlock_irqrestore(&gic_lock, flags); + + return 0; + } +@@ -537,12 +537,12 @@ static int gic_irq_domain_map(struct irq + if (!gic_local_irq_is_routable(intr)) + return -EPERM; + +- spin_lock_irqsave(&gic_lock, flags); ++ raw_spin_lock_irqsave(&gic_lock, flags); + for_each_online_cpu(cpu) { + write_gic_vl_other(mips_cm_vp_id(cpu)); + write_gic_vo_map(mips_gic_vx_map_reg(intr), map); + } +- spin_unlock_irqrestore(&gic_lock, flags); ++ raw_spin_unlock_irqrestore(&gic_lock, flags); + + return 0; + } diff --git a/queue-6.3/perf-x86-uncore-correct-the-number-of-chas-on-spr.patch b/queue-6.3/perf-x86-uncore-correct-the-number-of-chas-on-spr.patch new file mode 100644 index 00000000000..5a997e61bcb --- /dev/null +++ b/queue-6.3/perf-x86-uncore-correct-the-number-of-chas-on-spr.patch @@ -0,0 +1,58 @@ +From 38776cc45eb7603df4735a0410f42cffff8e71a1 Mon Sep 17 00:00:00 2001 +From: Kan Liang +Date: Mon, 8 May 2023 07:02:06 -0700 +Subject: perf/x86/uncore: Correct the number of CHAs on SPR + +From: Kan Liang + +commit 38776cc45eb7603df4735a0410f42cffff8e71a1 upstream. + +The number of CHAs from the discovery table on some SPR variants is +incorrect, because of a firmware issue. An accurate number can be read +from the MSR UNC_CBO_CONFIG. + +Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support") +Reported-by: Stephane Eranian +Signed-off-by: Kan Liang +Signed-off-by: Peter Zijlstra (Intel) +Tested-by: Stephane Eranian +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20230508140206.283708-1-kan.liang@linux.intel.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/events/intel/uncore_snbep.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +--- a/arch/x86/events/intel/uncore_snbep.c ++++ b/arch/x86/events/intel/uncore_snbep.c +@@ -6138,6 +6138,7 @@ static struct intel_uncore_type spr_unco + }; + + #define UNCORE_SPR_NUM_UNCORE_TYPES 12 ++#define UNCORE_SPR_CHA 0 + #define UNCORE_SPR_IIO 1 + #define UNCORE_SPR_IMC 6 + #define UNCORE_SPR_UPI 8 +@@ -6448,12 +6449,22 @@ static int uncore_type_max_boxes(struct + return max + 1; + } + ++#define SPR_MSR_UNC_CBO_CONFIG 0x2FFE ++ + void spr_uncore_cpu_init(void) + { ++ struct intel_uncore_type *type; ++ u64 num_cbo; ++ + uncore_msr_uncores = uncore_get_uncores(UNCORE_ACCESS_MSR, + UNCORE_SPR_MSR_EXTRA_UNCORES, + spr_msr_uncores); + ++ type = uncore_find_type_by_id(uncore_msr_uncores, UNCORE_SPR_CHA); ++ if (type) { ++ rdmsrl(SPR_MSR_UNC_CBO_CONFIG, num_cbo); ++ type->num_boxes = num_cbo; ++ } + spr_uncore_iio_free_running.num_boxes = uncore_type_max_boxes(uncore_msr_uncores, UNCORE_SPR_IIO); + } + diff --git a/queue-6.3/series b/queue-6.3/series index 90688d5cb73..1672cb51de3 100644 --- a/queue-6.3/series +++ b/queue-6.3/series @@ -53,3 +53,7 @@ binder-add-lockless-binder_alloc_-set-get-_vma.patch binder-fix-uaf-caused-by-faulty-buffer-cleanup.patch binder-fix-uaf-of-alloc-vma-in-race-with-munmap.patch drm-amd-amdgpu-limit-one-queue-per-gang.patch +perf-x86-uncore-correct-the-number-of-chas-on-spr.patch +x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch +irqchip-mips-gic-don-t-touch-vl_map-if-a-local-interrupt-is-not-routable.patch +irqchip-mips-gic-use-raw-spinlock-for-gic_lock.patch diff --git a/queue-6.3/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch b/queue-6.3/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch new file mode 100644 index 00000000000..85cad4c3d76 --- /dev/null +++ b/queue-6.3/x86-topology-fix-erroneous-smp_num_siblings-on-intel-hybrid-platforms.patch @@ -0,0 +1,90 @@ +From edc0a2b5957652f4685ef3516f519f84807087db Mon Sep 17 00:00:00 2001 +From: Zhang Rui +Date: Thu, 23 Mar 2023 09:56:40 +0800 +Subject: x86/topology: Fix erroneous smp_num_siblings on Intel Hybrid platforms + +From: Zhang Rui + +commit edc0a2b5957652f4685ef3516f519f84807087db upstream. + +Traditionally, all CPUs in a system have identical numbers of SMT +siblings. That changes with hybrid processors where some logical CPUs +have a sibling and others have none. + +Today, the CPU boot code sets the global variable smp_num_siblings when +every CPU thread is brought up. The last thread to boot will overwrite +it with the number of siblings of *that* thread. That last thread to +boot will "win". If the thread is a Pcore, smp_num_siblings == 2. If it +is an Ecore, smp_num_siblings == 1. + +smp_num_siblings describes if the *system* supports SMT. It should +specify the maximum number of SMT threads among all cores. + +Ensure that smp_num_siblings represents the system-wide maximum number +of siblings by always increasing its value. Never allow it to decrease. + +On MeteorLake-P platform, this fixes a problem that the Ecore CPUs are +not updated in any cpu sibling map because the system is treated as an +UP system when probing Ecore CPUs. + +Below shows part of the CPU topology information before and after the +fix, for both Pcore and Ecore CPU (cpu0 is Pcore, cpu 12 is Ecore). +... +-/sys/devices/system/cpu/cpu0/topology/package_cpus:000fff +-/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-11 ++/sys/devices/system/cpu/cpu0/topology/package_cpus:3fffff ++/sys/devices/system/cpu/cpu0/topology/package_cpus_list:0-21 +... +-/sys/devices/system/cpu/cpu12/topology/package_cpus:001000 +-/sys/devices/system/cpu/cpu12/topology/package_cpus_list:12 ++/sys/devices/system/cpu/cpu12/topology/package_cpus:3fffff ++/sys/devices/system/cpu/cpu12/topology/package_cpus_list:0-21 + +Notice that the "before" 'package_cpus_list' has only one CPU. This +means that userspace tools like lscpu will see a little laptop like +an 11-socket system: + +-Core(s) per socket: 1 +-Socket(s): 11 ++Core(s) per socket: 16 ++Socket(s): 1 + +This is also expected to make the scheduler do rather wonky things +too. + +[ dhansen: remove CPUID detail from changelog, add end user effects ] + +CC: stable@kernel.org +Fixes: bbb65d2d365e ("x86: use cpuid vector 0xb when available for detecting cpu topology") +Fixes: 95f3d39ccf7a ("x86/cpu/topology: Provide detect_extended_topology_early()") +Suggested-by: Len Brown +Signed-off-by: Zhang Rui +Signed-off-by: Dave Hansen +Acked-by: Peter Zijlstra (Intel) +Link: https://lore.kernel.org/all/20230323015640.27906-1-rui.zhang%40intel.com +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/topology.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/arch/x86/kernel/cpu/topology.c ++++ b/arch/x86/kernel/cpu/topology.c +@@ -79,7 +79,7 @@ int detect_extended_topology_early(struc + * initial apic id, which also represents 32-bit extended x2apic id. + */ + c->initial_apicid = edx; +- smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); ++ smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); + #endif + return 0; + } +@@ -109,7 +109,8 @@ int detect_extended_topology(struct cpui + */ + cpuid_count(leaf, SMT_LEVEL, &eax, &ebx, &ecx, &edx); + c->initial_apicid = edx; +- core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx); ++ core_level_siblings = LEVEL_MAX_SIBLINGS(ebx); ++ smp_num_siblings = max_t(int, smp_num_siblings, LEVEL_MAX_SIBLINGS(ebx)); + core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax); + die_level_siblings = LEVEL_MAX_SIBLINGS(ebx); + pkg_mask_width = die_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);