From: Eugen Hristev <eugen.hristev@microchip.com>
Date: Wed, 20 Oct 2021 09:46:54 +0000 (+0300)
Subject: ARM: dts: at91: sama7g5: add rtc node
X-Git-Tag: v5.16-rc1~125^2~5^2~2
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e79c58975c27d58d7683937538bcc6b547e1829d;p=thirdparty%2Flinux.git

ARM: dts: at91: sama7g5: add rtc node

Add RTC node.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers
 compared with sam9x60]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211020094656.3343242-2-claudiu.beznea@microchip.com
---

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index c9725d080e203..0912219ed5a16 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -130,6 +130,13 @@
 			reg = <0xe001d060 0x48>;
 		};
 
+		rtc: rtc@e001d0a8 {
+			compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
+			reg = <0xe001d0a8 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 1>;
+		};
+
 		ps_wdt: watchdog@e001d180 {
 			compatible = "microchip,sama7g5-wdt";
 			reg = <0xe001d180 0x24>;