From: zhongjuzhe <juzhe.zhong@rivai.ai>
Date: Tue, 30 Aug 2022 06:27:52 +0000 (+0800)
Subject: RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE
X-Git-Tag: basepoints/gcc-14~4877
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e8c83ab9d5142a305bbd75c7ff0e41eae38433df;p=thirdparty%2Fgcc.git

RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_conditional_register_usage): Add vector
	registers.
---

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 30cbf00542e9..675d92c0961b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5438,6 +5438,15 @@ riscv_conditional_register_usage (void)
       for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++)
 	call_used_regs[regno] = 1;
     }
+
+  if (!TARGET_VECTOR)
+    {
+      for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++)
+	fixed_regs[regno] = call_used_regs[regno] = 1;
+
+      fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1;
+      fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1;
+    }
 }
 
 /* Return a register priority for hard reg REGNO.  */