From: Zhao Qiang <qiang.zhao@nxp.com>
Date: Wed, 16 Sep 2020 03:03:10 +0000 (+0800)
Subject: clk: qoriq: modify MAX_PLL_DIV to 32
X-Git-Tag: v5.10-rc1~56^2~1^4
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e9501b975a9efb499f2ecbe3374d433b25c5b4f4;p=thirdparty%2Flinux.git

clk: qoriq: modify MAX_PLL_DIV to 32

On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 5942e9874bc08..46101c6a20f26 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -31,7 +31,7 @@
 #define CGA_PLL4	4	/* only on clockgen-1.0, which lacks CGB */
 #define CGB_PLL1	4
 #define CGB_PLL2	5
-#define MAX_PLL_DIV	16
+#define MAX_PLL_DIV	32
 
 struct clockgen_pll_div {
 	struct clk *clk;