From: Richard Henderson Date: Thu, 16 Aug 2018 13:05:27 +0000 (+0100) Subject: target/arm: Fix offset for LD1R instructions X-Git-Tag: v3.0.1~99 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=e97358cae4de99cbced24e487dabff53325ab5f0;p=thirdparty%2Fqemu.git target/arm: Fix offset for LD1R instructions The immediate should be scaled by the size of the memory reference, not the size of the elements into which it is loaded. Cc: qemu-stable@nongnu.org (3.0.1) Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues Signed-off-by: Peter Maydell (cherry picked from commit d0e372b0298f897993f831dbff7ad4f1c70f138e) Signed-off-by: Michael Roth --- diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9e63b5f8e55..f635822a613 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4819,6 +4819,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) unsigned vsz = vec_full_reg_size(s); unsigned psz = pred_full_reg_size(s); unsigned esz = dtype_esz[a->dtype]; + unsigned msz = dtype_msz(a->dtype); TCGLabel *over = gen_new_label(); TCGv_i64 temp; @@ -4842,7 +4843,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a, uint32_t insn) /* Load the data. */ temp = tcg_temp_new_i64(); - tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << esz); + tcg_gen_addi_i64(temp, cpu_reg_sp(s, a->rn), a->imm << msz); tcg_gen_qemu_ld_i64(temp, temp, get_mem_index(s), s->be_data | dtype_mop[a->dtype]);