From: Jernej Skrabec Date: Thu, 1 Mar 2018 21:34:31 +0000 (+0100) Subject: dt-bindings: display: sun4i-drm: Add compatibles for H3 HDMI pipeline X-Git-Tag: v4.17-rc1~185^2~16^2~52 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ea750c41467d9f42f9e358f85ab1a39c3baebac6;p=thirdparty%2Fkernel%2Flinux.git dt-bindings: display: sun4i-drm: Add compatibles for H3 HDMI pipeline Add missing compatibles for H3 HDMI pipeline. These compatibles can also be used with H5 SoC. Signed-off-by: Jernej Skrabec Signed-off-by: Maxime Ripard Link: https://patchwork.freedesktop.org/patch/msgid/20180301213442.16677-6-jernej.skrabec@siol.net --- diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index b995bfee734ae..8bdef4920edc4 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -102,6 +102,7 @@ DWC HDMI PHY Required properties: - compatible: value must be one of: * allwinner,sun8i-a83t-hdmi-phy + * allwinner,sun8i-h3-hdmi-phy - reg: base address and size of memory-mapped region - clocks: phandles to the clocks feeding the HDMI PHY * bus: the HDMI PHY interface clock @@ -110,6 +111,9 @@ Required properties: - resets: phandle to the reset controller driving the PHY - reset-names: must be "phy" +H3 HDMI PHY requires additional clock: + - pll-0: parent of phy clock + TV Encoder ---------- @@ -275,6 +279,7 @@ Required properties: - compatible: value must be one of: * allwinner,sun8i-a83t-de2-mixer-0 * allwinner,sun8i-a83t-de2-mixer-1 + * allwinner,sun8i-h3-de2-mixer-0 * allwinner,sun8i-v3s-de2-mixer - reg: base address and size of the memory-mapped region. - clocks: phandles to the clocks feeding the mixer @@ -305,6 +310,7 @@ Required properties: * allwinner,sun7i-a20-display-engine * allwinner,sun8i-a33-display-engine * allwinner,sun8i-a83t-display-engine + * allwinner,sun8i-h3-display-engine * allwinner,sun8i-v3s-display-engine - allwinner,pipelines: list of phandle to the display engine