From: Biju Das <biju.das.jz@bp.renesas.com>
Date: Wed, 22 Nov 2023 14:23:06 +0000 (+0000)
Subject: clk: versaclock3: Update vc3_get_div() to avoid divide by zero
X-Git-Tag: v6.8-rc1~106^2~3^2~4
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=eb16ddb838dd8602961b5fc17d1350cd41ae69e0;p=thirdparty%2Flinux.git

clk: versaclock3: Update vc3_get_div() to avoid divide by zero

Update vc3_get_div() to avoid divide by zero operation on
vc3_div_round_rate() by returning1, if there is no table match
found.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20231122142310.203169-2-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
---

diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c
index 00930d7bca778..3aad69a08512d 100644
--- a/drivers/clk/clk-versaclock3.c
+++ b/drivers/clk/clk-versaclock3.c
@@ -477,7 +477,7 @@ static unsigned int vc3_get_div(const struct clk_div_table *table,
 		if (clkt->val == val)
 			return clkt->div;
 
-	return 0;
+	return 1;
 }
 
 static unsigned long vc3_div_recalc_rate(struct clk_hw *hw,