From: Luis Pires Date: Wed, 2 Jun 2021 12:51:03 +0000 (-0300) Subject: target/ppc: fix single-step exception regression X-Git-Tag: v6.1.0-rc0~88^2 X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=eba3c766fe355a4e593c1ee6944770f80b68acad;p=thirdparty%2Fqemu.git target/ppc: fix single-step exception regression Commit 6086c75 (target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN) broke the generation of exceptions when CPU_SINGLE_STEP or CPU_BRANCH_STEP were set, due to nip always being reset to the address of the current instruction. This fix leaves nip untouched when generating the exception. Signed-off-by: Luis Pires Reported-by: Matheus Ferst Message-Id: <20210602125103.332793-1-luis.pires@eldorado.org.br> Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 95e4d9b8157..f65d1e81eac 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4320,8 +4320,7 @@ static void gen_lookup_and_goto_ptr(DisasContext *ctx) if (sse & GDBSTUB_SINGLE_STEP) { gen_debug_exception(ctx); } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { - uint32_t excp = gen_prep_dbgex(ctx); - gen_exception(ctx, excp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); } else { tcg_gen_exit_tb(NULL, 0); } @@ -8672,7 +8671,7 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) } /* else CPU_SINGLE_STEP... */ if (nip <= 0x100 || nip > 0xf00) { - gen_exception(ctx, gen_prep_dbgex(ctx)); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); return; } }