From: Dinh Nguyen <dinguyen@opensource.altera.com>
Date: Sat, 23 May 2015 04:00:10 +0000 (-0500)
Subject: ARM: socfpga: dts: add enable-method property for cpu nodes
X-Git-Tag: v4.2-rc1~99^2~16^2~3
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ebbce1bbc4f25c0ca68f66df54ea5e8eefa90da5;p=thirdparty%2Fkernel%2Flinux.git

ARM: socfpga: dts: add enable-method property for cpu nodes

Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index d9176e6061731..3a02b417ba873 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -36,6 +36,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "altr,socfpga-smp";
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 4cf0733b930b9..774e041b25722 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -36,6 +36,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "altr,socfpga-a10-smp";
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";