From: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Date: Tue, 12 Mar 2019 14:50:23 +0000 (+0530)
Subject: fpga: zynqpl: Flush dcache only for non-bitstream data
X-Git-Url: http://git.ipfire.org/?a=commitdiff_plain;h=ebf24fb076ce89bbdaa6a153df96a5474fec5271;p=thirdparty%2Fu-boot.git

fpga: zynqpl: Flush dcache only for non-bitstream data

In case of aes decryption destination address range must be flushed
before transferring decrypted data to destination.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index eabeb8aa873..e35d4921df8 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -541,7 +541,7 @@ int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
 	 * Flush destination address range only if image is not
 	 * bitstream.
 	 */
-	if (dstaddr != 0xFFFFFFFF)
+	if (bstype == BIT_NONE && dstaddr != 0xFFFFFFFF)
 		flush_dcache_range((u32)dstaddr, (u32)dstaddr +
 				   roundup(dstlen << 2, ARCH_DMA_MINALIGN));